B1.80 Memory Model Feature Register 0

The ID_MMFR0 characteristics are:

Purpose
Provides information about the memory model and memory management support in AArch32.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RO RO RO RO RO

Must be interpreted with ID_MMFR1, ID_MMFR2, and ID_MMFR3. See:

Configurations

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes
ID_MMFR0 is a 32-bit register.
Figure B1-35 ID_MMFR0 bit assignments
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InnerShr, [31:28]

Indicates the innermost shareability domain implemented:

0x1Implemented with hardware coherency support.
FCSE, [27:24]

Indicates support for Fast Context Switch Extension (FCSE):

0x0Not supported.
AuxReg, [23:20]

Indicates support for Auxiliary registers:

0x2Support for Auxiliary Fault Status Registers (AIFSR and ADFSR) and Auxiliary Control Register.
TCM, [19:16]

Indicates support for TCMs and associated DMAs:

0x0Not supported.
ShareLvl, [15:12]

Indicates the number of shareability levels implemented:

0x1Two levels of shareability implemented.
OuterShr, [11:8]

Indicates the outermost shareability domain implemented:

0x1Implemented with hardware coherency support.
PMSA, [7:4]

Indicates support for a Protected Memory System Architecture (PMSA):

0x0Not supported.
VMSA, [3:0]

Indicates support for a Virtual Memory System Architecture (VMSA).

0x5

Support for:

  • VMSAv7, with support for remapping and the Access flag.
  • The PXN bit in the Short-descriptor translation table format descriptors.
  • The Long-descriptor translation table format.

To access the ID_MMFR0:

MRC p15,0,<Rt>,c0,c1,4 ; Read ID_MMFR0 into Rt

Register access is encoded as follows:

Table B1-63 ID_MMFR0 access encoding

coproc opc1 CRn CRm opc2
1111 000 0000 0001 100
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