B1.81 Memory Model Feature Register 1

The ID_MMFR1 characteristics are:

Purpose
Provides information about the memory model and memory management support in AArch32.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RO RO RO RO RO

Must be interpreted with ID_MMFR0, ID_MMFR2, and ID_MMFR3. See:

Configurations

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes
ID_MMFR1 is a 32-bit register.
Figure B1-36 ID_MMFR1 bit assignments
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BPred, [31:28]

Indicates branch predictor management requirements:

0x4For execution correctness, branch predictor requires no flushing at any time.
L1TstCln, [27:24]

Indicates the supported L1 Data cache test and clean operations, for Harvard or unified cache implementation:

0x0None supported.
L1Uni, [23:20]

Indicates the supported entire L1 cache maintenance operations, for a unified cache implementation:

0x0None supported.
L1Hvd, [19:16]

Indicates the supported entire L1 cache maintenance operations, for a Harvard cache implementation:

0x0None supported.
L1UniSW, [15:12]

Indicates the supported L1 cache line maintenance operations by set/way, for a unified cache implementation:

0x0None supported.
L1HvdSW, [11:8]

Indicates the supported L1 cache line maintenance operations by set/way, for a Harvard cache implementation:

0x0None supported.
L1UniVA, [7:4]

Indicates the supported L1 cache line maintenance operations by MVA, for a unified cache implementation:

0x0None supported.
L1HvdVA, [3:0]

Indicates the supported L1 cache line maintenance operations by MVA, for a Harvard cache implementation:

0x0None supported.

To access the ID_MMFR1:

MRC p15, 0, <Rt>, c0, c1, 5; Read ID_MMFR1 into Rt

Register access is encoded as follows:

Table B1-64 ID_MMFR1 access encoding

coproc opc1 CRn CRm opc2
1111 000 0000 0001 101
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