B1.82 Memory Model Feature Register 2

The ID_MMFR2 characteristics are:

Purpose
Provides information about the implemented memory model and memory management support in AArch32.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RO RO RO RO RO

Must be interpreted with ID_MMFR0, ID_MMFR1, and ID_MMFR3. See:

Configurations

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes
ID_MMFR2 is a 32-bit register.
Figure B1-37 ID_MMFR2 bit assignments
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HWAccFlg, [31:28]

Hardware Access Flag. Indicates support for a Hardware Access flag, as part of the VMSAv7 implementation:

0x0Not supported.
WFIStall, [27:24]

Wait For Interrupt Stall. Indicates the support for Wait For Interrupt (WFI) stalling:

0x1Support for WFI stalling.
MemBarr, [23:20]

Memory Barrier. Indicates the supported CP15 memory barrier operations.

0x2

Supported CP15 memory barrier operations are:

  • Data Synchronization Barrier (DSB).
  • Instruction Synchronization Barrier (ISB).
  • Data Memory Barrier (DMB).
UniTLB, [19:16]

Unified TLB. Indicates the supported TLB maintenance operations, for a unified TLB implementation.

0x6

Supported unified TLB maintenance operations are:

  • Invalidate all entries in the TLB.
  • Invalidate TLB entry by MVA.
  • Invalidate TLB entries by ASID match.
  • Invalidate instruction TLB and data TLB entries by MVA All ASID. This is a shared unified TLB operation.
  • Invalidate Hyp mode unified TLB entry by MVA.
  • Invalidate entire Non-secure EL1 and EL0 unified TLB.
  • Invalidate entire Hyp mode unified TLB.
  • TLBIMVALIS, TLBIMVAALIS, TLBIMVALHIS, TLBIMVAL, TLBIMVAAL, and TLBIMVALH.
  • TLBIIPAS2IS, TLBIIPAS2LIS, TLBIIPAS2, and TLBIIPAS2L.
HvdTLB, [15:12]

Harvard TLB. Indicates the supported TLB maintenance operations, for a Harvard TLB implementation:

0x0

Not supported.

LL1HvdRng, [11:8]

L1 Harvard cache Range. Indicates the supported L1 cache maintenance range operations, for a Harvard cache implementation:

0x0Not supported.
L1HvdBG, [7:4]

L1 Harvard cache Background fetch. Indicates the supported L1 cache background prefetch operations, for a Harvard cache implementation:

0x0Not supported.
L1HvdFG, [3:0]

L1 Harvard cache Foreground fetch. Indicates the supported L1 cache foreground prefetch operations, for a Harvard cache implementation:

0x0Not supported.

To access the ID_MMFR2:

MRC p15,0,<Rt>,c0,c1,6 ; Read ID_MMFR2 into Rt

Register access is encoded as follows:

Table B1-65 ID_MMFR2 access encoding

coproc opc1 CRn CRm opc2
1111 000 0000 0001 110
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