B1.83 Memory Model Feature Register 3

The ID_MMFR3 characteristics are:

Purpose
Provides information about the memory model and memory management support in AArch32.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RO RO RO RO RO

Must be interpreted with ID_MMFR0, ID_MMFR1, and ID_MMFR2. See:

Configurations

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes
ID_MMFR3 is a 32-bit register.
Figure B1-38 ID_MMFR3 bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Supersec, [31:28]

Supersections. Indicates support for supersections:

0x0Supersections supported.
CMemSz, [27:24]

Cached Memory Size. Indicates the size of physical memory supported by the processor caches:

0x21TByte, corresponding to a 40-bit physical address range.
CohWalk, [23:20]

Coherent walk. Indicates whether translation table updates require a clean to the point of unification:

0x1Updates to the translation tables do not require a clean to the point of unification to ensure visibility by subsequent translation table walks.
[19:16]

Reserved, res0.

MaintBcst, [15:12]

Maintenance broadcast. Indicates whether cache, TLB and branch predictor operations are broadcast:

0x2Cache, TLB and branch predictor operations affect structures according to shareability and defined behavior of instructions.
BPMaint, [11:8]

Branch predictor maintenance. Indicates the supported branch predictor maintenance operations.

0x2

Supported branch predictor maintenance operations are:

  • Invalidate all branch predictors.
  • Invalidate branch predictors by MVA.
CMaintSW, [7:4]

Cache maintenance by set/way. Indicates the supported cache maintenance operations by set/way.

0x1

Supported hierarchical cache maintenance operations by set/way are:

  • Invalidate data cache by set/way.
  • Clean data cache by set/way.
  • Clean and invalidate data cache by set/way.
CMaintVA, [3:0]

Cache maintenance by MVA. Indicates the supported cache maintenance operations by MVA.

0x1

Supported hierarchical cache maintenance operations by MVA are:

  • Invalidate data cache by MVA.

    Invalidate data cache by MVA operations are treated as clean and invalidate data cache by MVA operations on the executing core. If the operation is broadcast to another core then it is broadcast as an invalidate data cache by MVA operation.

  • Clean data cache by MVA.
  • Clean and invalidate data cache by MVA.
  • Invalidate instruction cache by MVA.
  • Invalidate all instruction cache entries.

To access the ID_MMFR3:

MRC p15, 0, <Rt>, c0, c1, 7; Read ID_MMFR3 into Rt

Register access is encoded as follows:

Table B1-66 ID_MMFR3 access encoding

coproc opc1 CRn CRm opc2
1111 000 0000 0001 111
Non-ConfidentialPDF file icon PDF versionARM 100241_0001_00_en
Copyright © 2016, 2017 ARM Limited or its affiliates. All rights reserved.