B1.74 Instruction Set Attribute Register 0

The ID_ISAR0 characteristics are:

Purpose
Provides information about the instruction sets implemented by the processor in AArch32.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RO RO RO RO RO

Must be interpreted with ID_ISAR1, ID_ISAR2, ID_ISAR3, ID_ISAR4, and ID_ISAR5. See:

Configurations

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes
ID_ISAR0 is a 32-bit register.
Figure B1-29 ID_ISAR0 bit assignments
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[31:28]

Reserved, res0.

Divide, [27:24]

Indicates the implemented Divide instructions:

0x2
  • SDIV and UDIV in the T32 instruction set.
  • SDIV and UDIV in the A32 instruction set.
Debug, [23:20]

Indicates the implemented Debug instructions:

0x1BKPT.
Coproc, [19:16]

Indicates the implemented Coprocessor instructions:

0x0None implemented, except for separately attributed by the architecture including CP15, CP14, Advanced SIMD and floating-point.
CmpBranch, [15:12]

Indicates the implemented combined Compare and Branch instructions in the T32 instruction set:

0x1CBNZ and CBZ.
Bitfield, [11:8]

Indicates the implemented bit field instructions:

0x1BFC, BFI, SBFX, and UBFX.
BitCount, [7:4]

Indicates the implemented Bit Counting instructions:

0x1CLZ.
Swap, [3:0]

Indicates the implemented Swap instructions in the A32 instruction set:

0x0None implemented.

To access the ID_ISAR0:

MRC p15, 0, <Rt>, c0, c2, 0 ; Read ID_ISAR0 into Rt

Register access is encoded as follows:

Table B1-57 ID_ISAR0 access encoding

coproc opc1 CRn CRm opc2
1111 000 0000 0010 000
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