B1.76 Instruction Set Attribute Register 2

The ID_ISAR2 characteristics are:

Purpose
Provides information about the instruction sets implemented by the processor in AArch32.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RO RO RO RO RO

Must be interpreted with ID_ISAR0, ID_ISAR1, ID_ISAR3, ID_ISAR4 and ID_ISAR5. See.

Configurations

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes
ID_ISAR2 is a 32-bit register.
Figure B1-31 ID_ISAR2 bit assignments
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Reversal, [31:28]

Indicates the implemented Reversal instructions:

0x2

The REV, REV16, and REVSH instructions.

The RBIT instruction.

PSR_AR, [27:24]

Indicates the implemented A and R profile instructions to manipulate the PSR:

0x1The MRS and MSR instructions, and the exception return forms of data-processing instructions.

The exception return forms of the data-processing instructions are:

  • In the A32 instruction set, data-processing instructions with the PC as the destination and the S bit set.
  • In the T32 instruction set, the SUBS PC, LR, #N instruction.
MultU, [23:20]

Indicates the implemented advanced unsigned Multiply instructions:

0x2

The UMULL and UMLAL instructions.

The UMAAL instruction.

MultS, [19:16]

Indicates the implemented advanced signed Multiply instructions.

0x3
  • The SMULL and SMLAL instructions.
  • The SMLABB, SMLABT, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT instructions, and the Q bit in the PSRs.
  • The SMLAD, SMLADX, SMLALD, SMLALDX, SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR, SMMUL, SMMULR, SMUAD, SMUADX, SMUSD, and SMUSDX instructions.
Mult, [15:12]

Indicates the implemented additional Multiply instructions:

0x2

The MUL instruction.

The MLA instruction.

The MLS instruction.

MultiAccessInt, [11:8]

Indicates the support for interruptible multi-access instructions:

0x0No support. This means the LDM and STM instructions are not interruptible.
MemHint, [7:4]

Indicates the implemented memory hint instructions:

0x4

The PLD instruction.

The PLI instruction.

The PLDW instruction.

LoadStore, [3:0]

Indicates the implemented additional load/store instructions:

0x2

The LDRD and STRD instructions.

The Load Acquire (LDAB, LDAH, LDA, LDAEXB, LDAEXH, LDAEX, and LDAEXD) and Store Release (STLB, STLH, STL, STLEXB, STLEXH, STLEX, and STLEXD) instructions.

To access the ID_ISAR2:

MRC p15, 0, <Rt>, c0, c2, 2 ; Read ID_ISAR2 into Rt

Register access is encoded as follows:

Table B1-59 ID_ISAR2 access encoding

coproc opc1 CRn CRm opc2
1111 000 0000 0010 010
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