B1.77 Instruction Set Attribute Register 3

The ID_ISAR3 characteristics are:

Purpose
Provides information about the instruction sets implemented by the processor in AArch32.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RO RO RO RO RO

Must be interpreted with ID_ISAR0, ID_ISAR1, ID_ISAR2, ID_ISAR4, and ID_ISAR5. See:

Configurations

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes
ID_ISAR3 is a 32-bit register.
Figure B1-32 ID_ISAR3 bit assignments
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ThumbEE, [31:28]

Indicates the implemented Thumb Execution Environment (T32EE) instructions:

0x0None implemented.
TrueNOP, [27:24]

Indicates support for True NOP instructions:

0x1True NOP instructions in both the A32 and T32 instruction sets, and additional NOP-compatible hints.
ThumbCopy, [23:20]

Indicates the support for T32 non flag-setting MOV instructions:

0x1Support for T32 instruction set encoding T1 of the MOV (register) instruction, copying from a low register to a low register.
TabBranch, [19:16]

Indicates the implemented Table Branch instructions in the T32 instruction set.

0x1The TBB and TBH instructions.
SynchPrim, [15:12]

Indicates the implemented Synchronization Primitive instructions.

0x2
  • The LDREX and STREX instructions.
  • The CLREX, LDREXB, STREXB, and STREXH instructions.
  • The LDREXD and STREXD instructions.
SVC, [11:8]

Indicates the implemented SVC instructions:

0x1The SVC instruction.
SIMD, [7:4]

Indicates the implemented Single Instruction Multiple Data (SIMD) instructions.

0x3
  • The SSAT and USAT instructions, and the Q bit in the PSRs.
  • The PKHBT, PKHTB, QADD16, QADD8, QASX, QSUB16, QSUB8, QSAX, SADD16, SADD8, SASX, SEL, SHADD16, SHADD8, SHASX, SHSUB16, SHSUB8, SHSAX, SSAT16, SSUB16, SSUB8, SSAX, SXTAB16, SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UHASX, UHSUB16, UHSUB8, UHSAX, UQADD16, UQADD8, UQASX, UQSUB16, UQSUB8, UQSAX, USAD8, USADA8, USAT16, USUB16, USUB8, USAX, UXTAB16, UXTB16 instructions, and the GE[3:0] bits in the PSRs.
Saturate, [3:0]

Indicates the implemented Saturate instructions:

0x1The QADD, QDADD, QDSUB, QSUB and the Q bit in the PSRs.

To access the ID_ISAR3:

MRC p15, 0, <Rt>, c0, c2, 3 ; Read ID_ISAR3 into Rt

Register access is encoded as follows:

Table B1-60 ID_ISAR3 access encoding

coproc opc1 CRn CRm opc2
1111 000 0000 0010 011
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