B1.78 Instruction Set Attribute Register 4

The ID_ISAR4 characteristics are:

Purpose
Provides information about the instruction sets implemented by the processor in AArch32.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RO RO RO RO RO

Must be interpreted with ID_ISAR0, ID_ISAR1, ID_ISAR2, ID_ISAR3, and ID_ISAR5. See:

Configurations

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes
ID_ISAR4 is a 32-bit register.
Figure B1-33 ID_ISAR4 bit assignments
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SWP_frac, [31:28]

Indicates support for the memory system locking the bus for SWP or SWPB instructions:

0x0SWP and SWPB instructions not implemented.
PSR_M, [27:24]

Indicates the implemented M profile instructions to modify the PSRs:

0x0None implemented.
SynchPrim_frac, [23:20]

This field is used with the ID_ISAR3.SynchPrim field to indicate the implemented Synchronization Primitive instructions:

0x0
  • The LDREX and STREX instructions.
  • The CLREX, LDREXB, LDREXH, STREXB, and STREXH instructions.
  • The LDREXD and STREXD instructions.
Barrier, [19:16]

Indicates the supported Barrier instructions in the A32 and T32 instruction sets:

0x1The DMB, DSB, and ISB barrier instructions.
SMC, [15:12]

Indicates the implemented SMC instructions:

0x1The SMC instruction.
Writeback, [11:8]

Indicates the support for writeback addressing modes:

0x1Processor supports all of the writeback addressing modes defined in ARMv8.
WithShifts, [7:4]

Indicates the support for instructions with shifts:

0x4
  • Support for shifts of loads and stores over the range LSL 0-3.
  • Support for other constant shift options, both on load/store and other instructions.
  • Support for register-controlled shift options.
Unpriv, [3:0]

Indicates the implemented unprivileged instructions:

0x2
  • The LDRBT, LDRT, STRBT, and STRT instructions.
  • The LDRHT, LDRSBT, LDRSHT, and STRHT instructions.

To access the ID_ISAR4:

MRC p15, 0, <Rt>, c0, c2, 4 ; Read ID_ISAR4 into Rt

Register access is encoded as follows:

Table B1-61 ID_ISAR4 access encoding

coproc opc1 CRn CRm opc2
1111 000 0000 0010 100
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