B1.79 Instruction Set Attribute Register 5

The ID_ISAR5 characteristics are:

Purpose
Provides information about the instruction sets that the processor implements.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RO RO RO RO RO

ID_ISAR5 must be interpreted with ID_ISAR0, ID_ISAR1, ID_ISAR2, ID_ISAR3, and ID_ISAR4. See:

Configurations

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes
ID_ISAR5 is a 32-bit register.
Figure B1-34 ID_ISAR5 bit assignments
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[31:20]

Reserved, res0.

CRC32, [19:16]

Indicates whether CRC32 instructions are implemented in AArch32 state:

0x1CRC32 instructions are implemented.
SHA2, [15:12]

Indicates whether SHA2 instructions are implemented in AArch32 state:

0x0Cryptographic Extensions are not implemented or are disabled.
0x1SHA256H, SHA256H2, SHA256SU0, and SHA256SU1 instructions are implemented.

See the Cortex®‑A32 Processor Cryptographic Extension Technical Reference Manual for more information.

SHA1, [11:8]

Indicates whether SHA1 instructions are implemented in AArch32 state:

0x0Cryptographic Extensions are not implemented or are disabled.
0x1SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0, and SHA1SU1 instructions are implemented.

See the Cortex®‑A32 Processor Cryptographic Extension Technical Reference Manual for more information.

AES, [7:4]

Indicates whether AES instructions are implemented in AArch32 state:

0x0Cryptographic Extensions are not implemented or are disabled.
0x2AESE, AESD, AESMC and AESIMC, plus PMULL and PMULL2 instructions operating on 64-bit data.

See the Cortex®‑A32 Processor Cryptographic Extension Technical Reference Manual for more information.

SEVL, [3:0]

Indicates whether the SEVL instruction is implemented:

0x1SEVL implemented to send event local.

To access the ID_ISAR5:

MRC p15,0,<Rt>,c0,c2,5 ; Read ID_ISAR5 into Rt

Register access is encoded as follows:

Table B1-62 ID_ISAR5 access encoding

coproc opc1 CRn CRm opc2
1111 000 0000 0010 101
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