B1.40 Cache Level ID Register

The CLIDR characteristics are:

Purpose

Identifies:

  • The type of cache, or caches, implemented at each level.
  • The Level of Coherency and Level of Unification for the cache hierarchy.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RO RO RO RO RO
Configurations

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes
CLIDR is a 32-bit register.
Figure B1-4 CLIDR bit assignments
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ICB, [31:30]

Inner cache boundary. This field indicates the boundary between the inner and the outer domain.

0b00Not disclosed in this mechanism.
LoUU, [29:27]

Indicates the Level of Unification Uniprocessor for the cache hierarchy:

0b001L1 cache is the last level of cache that must be cleaned or invalidated when cleaning or invalidating to the point of unification for the processor.
LoC, [26:24]

Indicates the Level of Coherency for the cache hierarchy:

0b001L2 cache not implemented.
0b010A clean to the point of coherency operation requires the L1 and L2 caches to be cleaned.
LoUIS, [23:21]

Indicates the Level of Unification Inner Shareable for the cache hierarchy:

0b001

L2 cache not implemented or BROADCASTINNER set to 0.

The L1 cache is the last level of cache that must be cleaned or invalidated when cleaning or invalidating to the point of unification for the Inner Shareable shareability domain.

0b010

L2 cache implemented and BROADCASTINNER set to 1.

The L2 cache is the last level of cache that must be cleaned or invalidated when cleaning or invalidating to the point of unification for the Inner Shareable shareability domain.

[20:9]
Reserved, res0.
Ctype3, [8:6]

Indicates the type of cache if the processor implements L3 cache:

0b000L3 cache not implemented.

If software reads the Cache Type fields from Ctype1 upwards, after it has seen a value of 0b000, no caches exist at further-out levels of the hierarchy. So, for example, if Ctype2 is the first Cache Type field with a value of 0b000, the value of Ctype3 must be ignored.

Ctype2, [5:3]

Indicates the type of cache if the processor implements L2 cache:

0b000L2 cache is not implemented.
0b100L2 cache is implemented as a unified cache.
Ctype1, [2:0]

Indicates the type of cache implemented at L1:

0b011Separate instruction and data caches at L1.

To access the CLIDR:

MRC p15,1,<Rt>,c0,c0,1 ; Read CLIDR into Rt

Register access is encoded as follows:

Table B1-34 CLIDR access encoding

coproc opc1 CRn CRm opc2
1111 001 0000 0000 001
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