B1.45 Cache Size Selection Register

The CSSELR characteristics are:

Purpose

Selects the current CCSIDR, see B1.39 Cache Size ID Register, by specifying:

  • The required cache level.
  • The cache type, either instruction or data cache.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RW RW RW RW RW

If the CSSELR level field is programmed to a cache level that is not implemented, then a read of CSSELR returns an unknown value in CSSELR.Level.

Configurations

There are separate Secure and Non-secure instances of this register at EL3.

Attributes
CSSELR is a 32-bit register.
Figure B1-9 CSSELR bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


[31:4]

Reserved, res0.

Level, [3:1]

Cache level of required cache:

0b000L1.
0b001L2.
0b010-0b111Reserved.

The combination of Level=0b001 and InD=1 is reserved.

InD, [0]

Instruction not Data bit:

0Data or unified cache.
1Instruction cache.

The combination of Level=0b001 and InD=1 is reserved.

To access the CSSELR:

MRC p15, 2, <Rt>, c0, c0, 0; Read CSSELR into Rt
MCR p15, 2, <Rt>, c0, c0, 0; Write Rt to CSSELR

Register access is encoded as follows:

Table B1-39 CSSELR access encoding

coproc opc1 CRn CRm opc2
1111 010 0000 0001 000
Non-ConfidentialPDF file icon PDF versionARM 100241_0001_00_en
Copyright © 2016, 2017 ARM Limited or its affiliates. All rights reserved.