B1.46 Cache Type Register

The CTR characteristics are:

Purpose
Provides information about the architecture of the caches.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RO RO RO RO RO
Configurations

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes
CTR is a 32-bit register.
Figure B1-10 CTR bit assignments
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[31]

Reserved, res1.

[30:28]

Reserved, res0.

CWG, [27:24]

Cache Write-Back granule. Log2 of the number of words of the maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified:

0x4Cache Write-Back granule size is 16 words.
ERG, [23:20]

Exclusives Reservation Granule. Log2 of the number of words of the maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions:

0x4Exclusive reservation granule size is 16 words.
DminLine, [19:16]

Log2 of the number of words in the smallest cache line of all the data and unified caches that the processor controls:

0x4Smallest data cache line size is 16 words.
L1lp, [15:14]

L1 Instruction cache policy. Indicates the indexing and tagging policy for the L1 Instruction cache:

0b10Virtually Indexed Physically Tagged (VIPT).
[13:4]

Reserved, res0.

IminLine, [3:0]

Log2 of the number of words in the smallest cache line of all the instruction caches that the processor controls.

0x4Smallest instruction cache line size is 16 words.

To access the CTR:

MRC p15,0,<Rt>,c0,c0,1 ; Read CTR into Rt

Register access is encoded as follows:

Table B1-40 CTR access encoding

coproc opc1 CRn CRm opc2
1111 010 0000 0000 001
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