B1.105 System Control Register

The SCTLR characteristics are:

Purpose
Provides the top level control of the system, including its memory system.
Usage constraints

The SCTLR is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RW RW RW RW RW

Control bits in the SCTLR that are not applicable to a VMSA implementation read as the value that most closely reflects that implementation, and ignore writes.

Some bits in the register are read-only. These bits relate to non-configurable features of an implementation, and are provided for compatibility with previous versions of the architecture.

Configurations

There are separate Secure and Non-secure instances of this register at EL3.

Attributes
SCTLR is a 32-bit register.
Figure B1-58 SCTLR bit assignments
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[31]

Reserved, res0.

TE, [30]

T32 Exception enable. This bit controls whether exceptions are taken in A32 or T32 state:

0Exceptions, including reset, taken in A32 state.
1Exceptions, including reset, taken in T32 state.

The input CFGTE defines the reset value of the TE bit.

AFE, [29]

Access Flag Enable. This bit enables use of the AP[0] bit in the translation descriptors as the Access flag. It also restricts access permissions in the translation descriptors to the simplified model:

0In the translation table descriptors, AP[0] is an access permissions bit. The full range of access permissions is supported. No Access flag is implemented. This is the reset value.
1In the translation table descriptors, AP[0] is the Access flag. Only the simplified model for access permissions is supported.
TRE, [28]

TEX remap enable. This bit enables remapping of the TEX[2:1] bits for use as two translation table bits that can be managed by the operating system. Enabling this remapping also changes the scheme used to describe the memory region attributes in the VMSA:

0TEX remap disabled. TEX[2:0] are used, with the C and B bits, to describe the memory region attributes. This is the reset value.
1TEX remap enabled. TEX[2:1] are reassigned for use as bits managed by the operating system. The TEX[0], C and B bits are used to describe the memory region attributes, with the MMU remap registers.
[27:26]

Reserved, res0.

EE, [25]

Exception Endianness bit. The value of this bit defines the value of the CPSR.E bit on entry to an exception vector, including reset. This value also indicates the endianness of the translation table data for translation table lookups:

0Little endian.
1Big endian.

The input CFGEND defines the reset value of the EE bit.

[24]

Reserved, res0.

[23:22]

Reserved, res1.

[21]

Reserved, res0.

UWXN, [20]

Unprivileged write permission implies EL1 Execute Never (XN). This bit can be used to require all memory regions with unprivileged write permissions to be treated as XN for accesses from software executing at EL1.

0Regions with unprivileged write permission are not forced to be XN, this is the reset value.
1Regions with unprivileged write permission are forced to be XN for accesses from software executing at EL1.
WXN, [19]

Write permission implies Execute Never (XN). This bit can be used to require all memory regions with write permissions to be treated as XN.

0Regions with write permission are not forced to be XN, this is the reset value.
1Regions with write permissions are forced to be XN.
nTWE, [18]

Not trap WFE.

0If a WFE instruction executed at EL0 would cause execution to be suspended, such as if the event register is not set and there is not a pending WFE wakeup event, it is taken as an exception to EL1 using the 0x1 ESR code.
1WFE instructions are executed as normal.
[17]

Reserved, res0.

nTWI, [16]

Not trap WFI.

0If a WFI instruction executed at EL0 would cause execution to be suspended, such as if there is not a pending WFI wakeup event, it is taken as an exception to EL1 using the 0x1 ESR code.
1WFI instructions are executed as normal.
[15:14]

Reserved, res0.

V, [13]

Vectors bit. This bit selects the base address of the exception vectors:

0Normal exception vectors, base address 0x00000000. Software can remap this base address using the VBAR.
1High exception vectors, base address 0xFFFF0000. This base address is never remapped.

The input VINITHI defines the reset value of the V bit.

I, [12]

Instruction cache enable bit. This is a global enable bit for instruction caches:

0Instruction caches disabled. If SCTLR.M is set to 0, instruction accesses from stage 1 of the EL0/EL1 translation regime are to Normal memory, Outer Shareable, Inner Non-cacheable, Outer Non-cacheable.
1Instruction caches enabled. If SCTLR.M is set to 0, instruction accesses from stage 1 of the EL0/EL1 translation regime are to Normal memory, Outer Shareable, Inner Write-Through, Outer Write-Through.
[11]

Reserved, res1

[10:9]

Reserved, res0

SED, [8]

SETEND Disable:

0The SETEND instruction is available.
1The SETEND instruction is UNALLOCATED.
ITD, [7]

IT Disable:

0The IT instruction functionality is available.
1

All encodings of the IT instruction with hw1[3:0]!=1000 are undefined and treated as unallocated. All encodings of the subsequent instruction with the following values for hw1 are undefined (and treated as unallocated):

11xxxxxxxxxxxxxx

All 32-bit instructions, B(2), B(1), Undefined, SVC, Load/Store multiple

1x11xxxxxxxxxxxxMiscellaneous 16-bit instructions
1x100xxxxxxxxxxx ADD Rd, PC, #imm
01001xxxxxxxxxxxLDR Rd, [PC, #imm]
0100x1xxx1111xxxADD(4),CMP(3), MOV, BX pc, BLX pc
010001xx1xxxx111ADD(4),CMP(3), MOV
THEE, [6]
Reserved, res0.
CP15BEN, [5]

CP15 barrier enable.

0CP15 barrier operations disabled. Their encodings are undefined.
1CP15 barrier operations enabled.
[4:3]
Reserved, res1.
C, [2]

Cache enable. This is a global enable bit for data and unified caches:

0Data and unified caches disabled, this is the reset value.
1Data and unified caches enabled.
A, [1]

Alignment check enable. This is the enable bit for Alignment fault checking:

0Alignment fault checking disabled, this is the reset value.
1Alignment fault checking enabled.
M, [0]

MMU enable. This is a global enable bit for the MMU stage 1 address translation:

0EL1 and EL0 stage 1 MMU disabled.
1EL1 and EL0 stage 1 MMU enabled.

To access the SCTLR:

MRC p15, 0, <Rt>, c1, c0, 0 ; Read SCTLR into Rt
MCR p15, 0, <Rt>, c1, c0, 0 ; Write Rt to SCTLR

Register access is encoded as follows:

Table B1-90 SCTLR access encoding

coproc opc1 CRn CRm opc2
1111 000 0001 0000 000
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