B1.32 Auxiliary Control Register

The ACTLR characteristics are:

Purpose
Controls write access to implementation defined registers in EL2, such as CPUACTLR, CPUECTLR, L2CTLR, L2ECTLR, and L2ACTLR.
Usage constraints

This register is accessible as follows:

EL0

NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RW RW RW RW RW
Configurations

The processor does not implement the ACTLR (NS) register. This register is always res0.

Attributes
ACTLR is a 32-bit register.
Figure B1-1 ACTLR bit assignments
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[31:7]

Reserved, res0.

L2ACTLR access control, [6]

L2ACTLR write access control. The possible values are:

0The register is not write accessible from a lower exception level. This is the reset value.
1The register is write accessible from EL2.
L2ECTLR access control, [5]

L2ECTLR write access control. The possible values are:

0The register is not write accessible from a lower exception level. This is the reset value.
1The register is write accessible from EL2.
L2CTLR access control, [4]

L2CTLR write access control. The possible values are:

0The register is not write accessible from a lower exception level. This is the reset value.
1The register is write accessible from EL2.
[3:2]
Reserved, res0.
CPUECTLR access control, [1]

CPUECTLR write access control. The possible values are:

0The register is not write accessible from a lower exception level. This is the reset value.
1The register is write accessible from EL2.
CPUACTLR access control, [0]

CPUACTLR write access control. The possible values are:

0The register is not write accessible from a lower exception level. This is the reset value.
1The register is write accessible from EL2.

To access the ACTLR:

MRC p15, 0, <Rt>, c1, c0, 1 ; Read ACTLR into Rt
MCR p15, 0, <Rt>, c1, c0, 1 ; Write Rt to ACTLR

Register access is encoded as follows:

Table B1-30 ACTLR access encoding

coproc opc1 CRn CRm opc2
1111 000 0001 0000 001
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