B1.41 Architectural Feature Access Control Register

The CPACR characteristics are:

Purpose
Controls access to CP0 to CP13, and indicates which of CP0 to CP13 are implemented.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RW RW RW RW RW

The CPACR has no effect on instructions executed at EL2.

Configurations

There is one copy of this register that is used in both Secure and Non-secure states.

Bits in the NSACR control Non-secure access to the CPACR fields. See the field descriptions cp10 and cp11.

Attributes
CPACR is a 32-bit register.
Figure B1-5 CPACR bit assignments
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ASEDIS, [31]

Disable Advanced SIMD functionality:

0Does not cause any instructions to be undefined. This is the reset value.
1All instruction encodings that are part of Advanced SIMD, but that are not floating-point instructions, are undefined.

If Advanced SIMD and floating-point are not implemented, this bit is res0.

[30:24]

Reserved, res0.

cp11, [23:22]

Defines the access rights for CP11, that control the Advanced SIMD and floating-point features. Possible values of the fields are:

0b00Access denied. Any attempt to access Advanced SIMD and floating-point registers or instructions generates an Undefined Instruction exception. This is the reset value.
0b01Access at EL1 only. Any attempt to access Advanced SIMD and floating-point registers or instructions from software executing at EL0 generates an Undefined Instruction exception.
0b10Reserved.
0b11Full access.

If Advanced SIMD and floating-point are not implemented, this field is res0.

The Advanced SIMD and floating-point features controlled by these fields are:

  • Floating-point instructions.
  • Advanced SIMD instructions, both integer and floating-point.
  • Advanced SIMD and floating-point registers D0-D31 and their views as S0-S31 and Q0-Q15.
  • FPSCR, FPSID, MVFR0, MVFR1, MVFR2, FPEXC system registers.

If the cp11 and cp10 fields are set to different values, the behavior is the same as if both fields were set to the value of cp10, in all respects other than the value read back by explicitly reading cp11.

cp10, [21:20]

Defines the access rights for CP10, that control the Advanced SIMD and floating-point features. Possible values of the fields are:

0b00Access denied. Any attempt to access Advanced SIMD and floating-point registers or instructions generates an Undefined Instruction exception. This is the reset value.
0b01Access at EL1 only. Any attempt to access Advanced SIMD and floating-point registers or instructions from software executing at EL0 generates an Undefined Instruction exception.
0b10Reserved.
0b11Full access.

If Advanced SIMD and floating-point are not implemented, this bit is res0.

The Advanced SIMD and floating-point features controlled by these fields are:

  • Floating-point instructions.
  • Advanced SIMD instructions, both integer and floating-point.
  • Advanced SIMD and floating-point registers D0-D31 and their views as S0-S31 and Q0-Q15.
  • FPSCR, FPSID, MVFR0, MVFR1, MVFR2, FPEXC system registers.
[19:0]

Reserved, res0.

To access the CPACR:

MRC p15,0,<Rt>,c1,c0,2 ; Read CPACR into Rt
MCR p15,0,<Rt>,c1,c0,2 ; Write Rt to CPACR

Register access is encoded as follows:

Table B1-35 CPACR access encoding

coproc opc1 CRn CRm opc2
1111 000 0001 0000 010
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