B1.104 Secure Configuration Register

The SCR characteristics are:

Purpose

Defines the configuration of the current security state. It specifies:

  • The security state of the processor, Secure or Non-secure.
  • What state the processor branches to, if an IRQ, FIQ or external abort occurs.
  • Whether the CPSR.F and CPSR.A bits can be modified when SCR.NS = 1.
Usage constraints

This register is accessible as follows:

EL0

NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - RW - RW RW

Any read or write to SCR in Secure EL1 state in AArch32 is trapped as an exception to EL3.

Configurations

The SCR is a Restricted access register that exists only in the Secure state.

Attributes
SCR is a 32-bit register.
Figure B1-57 SCR bit assignments
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[31:14]

Reserved, res0.

TWE, [13]

Trap WFE instructions. The possible values are:

0WFE instructions are not trapped. This is the reset value.
1

WFE instructions executed in any mode other than Monitor mode are trapped to Monitor mode as undefined if the instruction would otherwise cause suspension of execution, that is if:

  • The event register is not set.
  • There is not a pending WFE wakeup event.
  • The instruction does not cause another exception.
TWI, [12]

Trap WFI instructions. The possible values are:

0

WFI instructions are not trapped. This is the reset value.

1WFI instructions executed in any mode other than Monitor mode are trapped to Monitor mode as undefined if the instruction would otherwise cause suspension of execution.
[11:10]

Reserved, res0.

SIF, [9]

Secure Instruction Fetch. When the processor is in Secure state, this bit disables instruction fetches from Non-secure memory. The possible values are:

0Secure state instruction fetches from Non-secure memory permitted. This is the reset value.
1Secure state instruction fetches from Non-secure memory not permitted.
HCE, [8]

Hyp Call enable. This bit enables use of the HVC instruction from Non-secure EL1 modes. The possible values are:

0The HVC instruction is undefined in any mode. This is the reset value.
1The HVC instruction enabled in Non-secure EL1, and performs a Hyp Call.
SCD, [7]

Secure Monitor Call disable. Makes the SMC instruction undefined in Non-secure state. The possible values are:

0SMC executes normally in Non-secure state, performing a Secure Monitor Call. This is the reset value.
1The SMC instruction is undefined in Non-secure state.

A trap of the SMC instruction to Hyp mode takes priority over the value of this bit.

nET, [6]

Not Early Termination. This bit disables early termination.

This bit is not implemented, res0.

AW, [5]

A bit writable. This bit controls whether CPSR.A can be modified in Non-secure state.

  • CPSR.A can be modified only in Secure state. This is the reset value.
  • CPSR.A can be modified in any security state.
FW, [4]

F bit writable. This bit controls whether CPSR.F can be modified in Non-secure state:

  • CPSR.F can be modified only in Secure state. This is the reset value.
  • CPSR.F can be modified in any security state.
EA, [3]

External Abort handler. This bit controls which mode takes external aborts. The possible values are:

0External aborts taken in abort mode. This is the reset value.
1External aborts taken in Monitor mode.
FIQ, [2]

FIQ handler. This bit controls which mode takes FIQ exceptions. The possible values are:

0FIQs taken in FIQ mode. This is the reset value.
1FIQs taken in Monitor mode.
IRQ, [1]

IRQ handler. This bit controls which mode takes IRQ exceptions. The possible values are:

0IRQs taken in IRQ mode. This is the reset value.
1IRQs taken in Monitor mode.
NS, [0]

Non-secure bit. Except when the processor is in Monitor mode, this bit determines the security state of the processor. The possible values are:

0Processor is in secure state. This is the reset value.
1Processor is in non-secure state.

To access the SCR:

MRC p15,0,<Rt>,c1,c1,0 ; Read SCR into Rt
MCR p15,0,<Rt>,c1,c1,0 ; Write Rt to SCR

Register access is encoded as follows:

Table B1-89 SCR access encoding

coproc opc1 CRn CRm opc2
1111 000 0001 0001 000
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