B1.106 Secure Debug Control Register

The SDCR characteristics are:

Purpose
Controls debug and performance monitors functionality in Secure state.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - RW - RW RW
Configurations
There are no configuration notes.
Attributes
SDCR is a 32-bit register.
Figure B1-59 SDCR bit assignments
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[31:22]

Reserved, res0.

EPMAD, [21]

External debugger access to Performance Monitors registers disabled. This disables access to these registers by an external debugger:

0Access to Performance Monitors registers from external debugger is permitted. This is the reset value.
1Access to Performance Monitors registers from external debugger is disabled, unless overridden by authentication interface.
EDAD, [20]

External debugger access to breakpoint and watchpoint registers disabled. This disables access to these registers by an external debugger:

0Access to breakpoint and watchpoint registers from external debugger is permitted. This is the reset value.
1Access to breakpoint and watchpoint registers from external debugger is disabled, unless overridden by authentication interface.
[19:18]

Reserved, res0.

SPME, [17]

Secure performance monitors enable. This allows event counting in Secure state:

0Event counting prohibited in Secure state, unless overridden by the authentication interface. This is the reset value.
1Event counting allowed in Secure state.
[16]

Reserved, res0.

SPD, [15:14]

AArch32 secure privileged debug. Enables or disables debug exceptions in Secure state, other than Software breakpoint instructions. The possible values are:

0b00Legacy mode. Debug exceptions from Secure EL1 are enabled by the authentication interface.
0b10Secure privileged debug disabled. Debug exceptions from Secure EL1 are disabled.
0b11Secure privileged debug enabled. Debug exceptions from Secure EL1 are enabled.

The value 0b01 is reserved.

If debug exceptions from Secure EL1 are enabled, then debug exceptions from Secure EL0 are also enabled.

Otherwise, debug exceptions from Secure EL0 are enabled only if SDER32_EL3.SUIDEN is 1.

SPD is ignored in Non-secure state. Debug exceptions from Software breakpoint instruction debug events are always enabled.

[13:0]

Reserved, res0.

To access the SDCR:

MRC p15,0,<Rt>,c1,c3,1 ; Read SDCR into Rt
MCR p15,0,<Rt>,c1,c3,1 ; Write Rt to SDCR

Register access is encoded as follows:

Table B1-91 SDCR access encoding

coproc opc1 CRn CRm opc2
1111 000 0001 0011 001
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