B1.55 Hyp Auxiliary Control Register

The HACTLR characteristics are:

Purpose
Controls write access to implementation defined registers in Non-secure EL1 modes, such as CPUACTLR, CPUECTLR, L2CTLR, L2ECTLR, and L2ACTLR.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - - RW RW -
Configurations
There are no configuration notes.
Attributes
HACTLR is a 32-bit register.
Figure B1-15 HACTLR bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


[31:7]

Reserved, res0.

L2ACTLR access control, [6]

L2ACTLR write access control. The possible values are:

0

The register is not write accessible from Non-secure EL1.

This is the reset value.

1

The register is write accessible from Non-secure EL1.

Write access from Non-secure EL1 also requires ACTLR(S)[6] to be set.

L2ECTLR access control, [5]

L2ECTLR write access control. The possible values are:

0

The register is not write accessible from Non-secure EL1.

This is the reset value.

1

The register is write accessible from Non-secure EL1.

Write access from Non-secure EL1 also requires ACTLR(S)[5] to be set.

L2CTLR access control, [4]

L2CTLR write access control. The possible values are:

0

The register is not write accessible from Non-secure EL1.

This is the reset value.

1

The register is write accessible from Non-secure EL1.

Write access from Non-secure EL1 also requires ACTLR(S)[4] to be set.

[3:2]

Reserved, res0.

CPUECTLR access control, [1]

CPUECTLR write access control. The possible values are:

0

The register is not write accessible from Non-secure EL1.

This is the reset value.

1

The register is write accessible from Non-secure EL1.

Write access from Non-secure EL1 also requires ACTLR(S)[1] to be set.

CPUACTLR access control, [0]

CPUACTLR write access control. The possible values are:

0

The register is not write accessible from Non-secure EL1.

This is the reset value.

1

The register is write accessible from Non-secure EL1.

Write access from Non-secure EL1 also requires ACTLR(S)[0] to be set.

To access the HACTLR:

MRC p15,4,<Rt>,c1,c0,1 ; Read HACTLR into Rt
MCR p15,4,<Rt>,c1,c0,1 ; Write Rt to HACTLR

Register access is encoded as follows:

Table B1-44 HACTLR access encoding

coproc opc1 CRn CRm opc2
1111 100 0001 0000 001
Non-ConfidentialPDF file icon PDF versionARM 100241_0001_00_en
Copyright © 2016, 2017 ARM Limited or its affiliates. All rights reserved.