B1.67 Hyp System Control Register

The HSCTLR characteristics are:

Purpose
Provides top level control of the system operation in Hyp mode. This register provides Hyp mode control of features controlled by the Banked SCTLR bits, and shows the values of the non-Banked SCTLR bits.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - - RW RW -
Configurations
There are no configuration notes.
Attributes
HSCTLR is a 32-bit register.
Figure B1-23 HSCTLR bit assignments
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[31]

Reserved, res0.

TE, [30]

Thumb Exception enable. This bit controls whether exceptions taken in Hyp mode are taken in A32 or T32 state:

0Exceptions taken in A32 state.
1Exceptions taken in T32 state.
[29:28]

Reserved, res1.

[27:26]

Reserved, res0.

EE, [25]

Exception Endianness. The value of this bit defines the value of the CPSR.E bit on entry to an exception vector, including reset. This value also indicates the endianness of the translation table data for translation table lookups:

0Little endian.
1Big endian.
[24]

Reserved, res0.

[23:22]

Reserved, res1.

FI, [21]

Fast Interrupts configuration enable bit. This bit can be used to reduce interrupt latency by disabling implementation-defined performance features.

This bit is not implemented, res0.

[20]

Reserved, res0.

WXN, [19]

Write permission implies Execute Never (XN). This bit can be used to require all memory regions with write permission to be treated as XN:

0Regions with write permission are not forced to XN.
1Regions with write permission are forced to XN.

The WXN bit is permitted to be cached in a TLB.

[18]

Reserved, res1.

[17]

Reserved, res0.

[16]

Reserved, res1.

[15:13]

Reserved, res0.

I, [12]

Instruction cache enable. This is an enable bit for instruction caches at EL2:

0Instruction caches disabled at EL2. If HSCTLR.M is set to 0, instruction accesses from stage 1 of the EL2 translation regime are to Normal memory, Outer Shareable, Inner Non-cacheable, Outer Non-cacheable.
1Instruction caches enabled at EL2. If HSCTLR.M is set to 0, instruction accesses from stage 1 of the EL2 translation regime are to Normal memory, Outer Shareable, Inner Write-Through, Outer Write-Through.

When this bit is 0, all EL2 Normal memory instruction accesses are Non-cacheable.

If this register is at the highest exception level implemented, field resets to 0. Otherwise, its reset value is unknown.

[11]

Reserved, res1.

[10:9]

Reserved, res0.

SED, [8]

SETEND Disable:

0The SETEND instruction is available.
1The SETEND instruction is UNALLOCATED.
ITD, [7]

IT Disable:

0The IT instruction functionality is available.
1

All encodings of the IT instruction with hw1[3:0]!=1000 are undefined and treated as unallocated. All encodings of the subsequent instruction with the following values for hw1 are undefined (and treated as unallocated):

11xxxxxxxxxxxxxx

All 32-bit instructions, B(2), B(1), Undefined, SVC, Load/Store multiple

1x11xxxxxxxxxxxxMiscellaneous 16-bit instructions
1x100xxxxxxxxxx ADD Rd, PC, #imm
01001xxxxxxxxxxxLDR Rd, [PC, #imm]
0100x1xxx1111xxxADD(4),CMP(3), MOV, BX pc, BLX pc
010001xx1xxxx111ADD(4),CMP(3), MOV
[6]

Reserved, res0.

CP15BEN, [5]

CP15 barrier enable:

0CP15 barrier operations disabled. Their encodings are undefined.
1CP15 barrier operations enabled.
[4:3]

Reserved, res1.

C, [2]

Cache enable. This is an enable bit for data and unified caches at EL2:

0Data and unified caches disabled at EL2.
1Data and unified caches enabled at EL2.

When this bit is 0, all EL2 Normal memory data accesses and all accesses to the EL2 translation tables are Non-cacheable.

If this register is at the highest exception level implemented, field resets to 0. Otherwise, its reset value is unknown.

A, [1]

Alignment check enable. This is the enable bit for Alignment fault checking:

0Alignment fault checking disabled.
1Alignment fault checking enabled.

When this bit is 1, all instructions that load or store one or more registers, other than load/store exclusive and load-acquire/store-release, have an alignment check that the address being accessed is aligned to the size of the data element(s) being accessed. If this check fails it causes an Alignment fault, that is taken as a Data Abort exception.

Load/store exclusive and load-acquire/store-release instructions have this alignment check regardless of the value of the A bit.

If this register is at the highest exception level implemented, field resets to 0. Otherwise, its reset value is unknown.

M, [0]

MMU enable. This is a global enable bit for the EL2 stage 1 MMU:

0EL2 stage 1 MMU disabled.
1EL2 stage 1 MMU enabled.

If this register is at the highest exception level implemented, field resets to 0. Otherwise, its reset value is unknown.

To access the HSCTLR:

MRC p15,4,<Rt>,c1,c0,0 ; Read HSCTLR into Rt
MCR p15,4,<Rt>,c1,c0,0 ; Write Rt to HSCTLR

Register access is encoded as follows:

Table B1-52 HSCTLR access encoding

coproc opc1 CRn CRm opc2
1111 100 0001 0000 000
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