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TTBR1 has a specific format when using the Short-descriptor translation table format. TTBCR.EAE determines which format of the register is in use.
The following figure shows the TTBR1 bit assignments when TTBCR.EAE is 0.
Translation table base 1 address, bits[31:x], where x is 14-(TTBCR.N). Bits [x-1:7] are res0.
The translation table must be aligned on a 16KByte boundary.
If bits [x-1:7] are not all zero, this is a misaligned Translation Table Base Address. Its effects are constrained unpredictable, where bits [x-1:7] are treated as if all the bits are zero. The value read back from those bits is the value written.
See IRGN below for description of the IRGN field.
Not Outer Shareable bit. Indicates the Outer Shareable attribute for the memory associated with a translation table walk that has the Shareable attribute, indicated by TTBR0.S is 1. The possible values are:
This bit is ignored when TTBR0.S is 0.
Region bits. Indicates the Outer cacheability attributes for the memory associated with the translation table walks. The possible values are:
|Normal memory, Outer Non-cacheable.|
|Normal memory, Outer Write-Back Write-Allocate Cacheable.|
|Normal memory, Outer Write-Through Cacheable.|
|Normal memory, Outer Write-Back no Write-Allocate Cacheable.|
Shareable bit. Indicates the Shareable attribute for the memory associated with the translation table walks. The possible values are:
Inner region bits. Indicates the Inner Cacheability attributes for the memory associated with the translation table walks. The possible values of IRGN[1:0] are:
|Normal memory, Inner Non-cacheable.|
|Normal memory, Inner Write-Back Write-Allocate Cacheable.|
|Normal memory, Inner Write-Through Cacheable.|
|Normal memory, Inner Write-Back no Write-Allocate Cacheable.|
The encoding of the IRGN bits is counter-intuitive, with register bit being IRGN and register bit being IRGN. This encoding is chosen to give a consistent encoding of memory region types and to ensure that software written for ARMv7 without the Multiprocessing Extensions can run unmodified on an implementation that includes the functionality introduced by the ARMv7 Multiprocessing Extensions.
To access the TTBR1 when TTBCR.EAE is 0:
MRC p15, 0, <Rt>, c2, c0, 1 ; Read TTBR1 into Rt MCR p15, 0, <Rt>, c2, c0, 1 ; Write Rt to TTBR1
Register access is encoded as follows:
Table B1-96 TTBR1 access encoding