B1.70 Hyp Translation Control Register

The HTCR characteristics are:

Purpose
Controls translation table walks required for the stage 1 translation of memory accesses from Hyp mode, and holds cacheability and shareability information for the accesses.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - - RW RW -
Configurations
There are no configuration notes.
Attributes
HTCR is a 32-bit register.
Figure B1-26 HTCR bit assignments
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[31]

Reserved, res1.

[30:24]
Reserved, res0.
[23]

Reserved, res1.

[22:14]
Reserved, res0.
SH0, [13:12]

Shareability attribute for memory associated with translation table walks using TTBR0. The possible values are:

0b00Non-shareable.
0b01Reserved.
0b10Outer shareable.
0b11Inner shareable.
ORGN0, [11:10]

Outer cacheability attribute for memory associated with translation table walks using TTBR0. The possible values are:

0b00Normal memory, Outer Non-cacheable.
0b01Normal memory, Outer Write-Back Write-Allocate Cacheable.
0b10Normal memory, Outer Write-Through Cacheable.
0b11Normal memory, Outer Write-Back no Write-Allocate Cacheable.
IRGN0, [9:8]

Inner cacheability attribute for memory associated with translation table walks using TTBR0. The possible values are:

0b00Normal memory, Inner Non-cacheable.
0b01Normal memory, Inner Write-Back Write-Allocate Cacheable.
0b10Normal memory, Inner Write-Through Cacheable.
0b11Normal memory, Inner Write-Back no Write-Allocate Cacheable.
[7:3]

Reserved, res0.

T0SZ, [2:0]

Size offset of the memory region addressed by TTBR0. The region size is 2(32-TSIZE) bytes.

The processor does not use the implementation-defined bit, HTCR[30], so this bit is res0.

To access the HTCR:

MRC p15, 4, <Rt>, c2, c0, 2; Read HTCR into Rt
MCR p15, 4, <Rt>, c2, c0, 2; Write Rt to HTCR

Register access is encoded as follows:

Table B1-54 HTCR access encoding

coproc opc1 CRn CRm opc2
1111 100 0010 0000 010
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