B1.122 Virtualization Translation Control Register

The VTCR characteristics are:

Purpose
Controls the translation table walks required for the stage 2 translation of memory accesses from Non-secure modes other than Hyp mode, and holds cacheability and shareability information for the accesses.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - - RW RW -

Used in conjunction with VTTBR, that defines the translation table base address for the translations.

Configurations

This register is accessible only at EL2 or EL3.

Attributes
VTCR is a 32-bit register.
Figure B1-70 VTCR bit assignments
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[31]

Reserved, res1.

[30:14]

Reserved, res0.

SH0, [13:12]

Shareability attribute for memory associated with translation table walks using TTBR0.

0b00Non-shareable.
0b01Reserved.
0b10Outer Shareable.
0b11Inner Shareable.
ORGN0, [11:10]

Outer cacheability attribute for memory associated with translation table walks using TTBR0.

0b00Normal memory, Outer Non-cacheable.
0b01Normal memory, Outer Write-Back Write-Allocate Cacheable.
0b10Normal memory, Outer Write-Through Cacheable.
0b11Normal memory, Outer Write-Back no Write-Allocate Cacheable.
IRGN0, [9:8]

Inner cacheability attribute for memory associated with translation table walks using TTBR0.

0b00Normal memory, Inner Non-cacheable.
0b01Normal memory, Inner Write-Back Write-Allocate Cacheable.
0b10Normal memory, Inner Write-Through Cacheable.
0b11Normal memory, Inner Write-Back no Write-Allocate Cacheable.
SL0, [7:6]

Starting level for translation table walks using VTTBR:

0b00Start at second level.
0b01Start at first level.
[5]
Reserved, res0.
S, [4]
Sign extension bit. This bit must be programmed to the value of T0SZ[3]. If it is not, then the stage 2 T0SZ value is treated as an unknown value within the legal range that can be programmed.
T0SZ, [3:0]

The size offset of the memory region addressed by TTBR0. The region size is 232-T0SZ bytes.

To access the VTCR:

MRC p15, 4, <Rt>, c2, c1, 2; Read VTCR into Rt
MCR p15, 4, <Rt>, c2, c1, 2; Write Rt to VTCR

Register access is encoded as follows:

Table B1-101 VTCR access encoding

coproc opc1 CRn CRm opc2
1111 100 0010 0001 010
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