B1.69 Hyp System Trap Register

The HSTR characteristics are:

Purpose
Controls trapping to Hyp mode of Non-secure accesses, at EL1 or lower, of use of T32EE, or the CP15 primary registers, {c0-c3,c5-c13,c15}.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - - RW RW -
Configurations

This register is accessible only at EL2 or EL3.

Attributes
HSTR is a 32-bit register.
Figure B1-25 HSTR bit assignments
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[31:17]

Reserved, res0.

TTEE, [16]

Trap T32EE. This value is:

0T32EE is not supported.
T15, [15]

Trap coprocessor primary register CRn = 15. The possible values are:

0Has no effect on Non-secure accesses to CP15 registers.
1Trap valid Non-secure accesses to coprocessor primary register CRn = 15 to Hyp mode.

The reset value is 0.

[14]

Reserved, res0.

T13, [13]

Trap coprocessor primary register CRn = 13. The possible values are:

0Has no effect on Non-secure accesses to CP15 registers.
1Trap valid Non-secure accesses to coprocessor primary register CRn = 13 to Hyp mode.

The reset value is 0.

T12, [12]

Trap coprocessor primary register CRn = 12. The possible values are:

0Has no effect on Non-secure accesses to CP15 registers.
1Trap valid Non-secure accesses to coprocessor primary register CRn = 12 to Hyp mode.

The reset value is 0.

T11, [11]

Trap coprocessor primary register CRn = 11. The possible values are:

0Has no effect on Non-secure accesses to CP15 registers.
1Trap valid Non-secure accesses to coprocessor primary register CRn = 11 to Hyp mode.

The reset value is 0.

T10, [10]

Trap coprocessor primary register CRn = 10. The possible values are:

0Has no effect on Non-secure accesses to CP15 registers.
1Trap valid Non-secure accesses to coprocessor primary register CRn = 10 to Hyp mode.

The reset value is 0.

T9, [9]

Trap coprocessor primary register CRn = 9. The possible values are:

0Has no effect on Non-secure accesses to CP15 registers.
1Trap valid Non-secure accesses to coprocessor primary register CRn = 9 to Hyp mode.

The reset value is 0.

T8, [8]

Trap coprocessor primary register CRn = 8. The possible values are:

0Has no effect on Non-secure accesses to CP15 registers.
1Trap valid Non-secure accesses to coprocessor primary register CRn = 8 to Hyp mode.

The reset value is 0.

T7, [7]

Trap coprocessor primary register CRn = 7. The possible values are:

0Has no effect on Non-secure accesses to CP15 registers.
1Trap valid Non-secure accesses to coprocessor primary register CRn = 7 to Hyp mode.

The reset value is 0.

T6, [6]

Trap coprocessor primary register CRn = 6. The possible values are:

0Has no effect on Non-secure accesses to CP15 registers.
1Trap valid Non-secure accesses to coprocessor primary register CRn = 6 to Hyp mode.

The reset value is 0.

T5, [5]

Trap coprocessor primary register CRn = 5. The possible values are:

0Has no effect on Non-secure accesses to CP15 registers.
1Trap valid Non-secure accesses to coprocessor primary register CRn = 5 to Hyp mode.

The reset value is 0.

[4]
Reserved, res0.
T3, [3]

Trap coprocessor primary register CRn = 3. The possible values are:

0Has no effect on Non-secure accesses to CP15 registers.
1Trap valid Non-secure accesses to coprocessor primary register CRn = 3 to Hyp mode.

The reset value is 0.

T2, [2]

Trap coprocessor primary register CRn = 2. The possible values are:

0Has no effect on Non-secure accesses to CP15 registers.
1Trap valid Non-secure accesses to coprocessor primary register CRn = 2 to Hyp mode.

The reset value is 0.

T1, [1]

Trap coprocessor primary register CRn = 1. The possible values are:

0Has no effect on Non-secure accesses to CP15 registers.
1Trap valid Non-secure accesses to coprocessor primary register CRn = 1 to Hyp mode.

The reset value is 0.

T0, [0]

Trap coprocessor primary register CRn = 0. The possible values are:

0Has no effect on Non-secure accesses to CP15 registers.
1Trap valid Non-secure accesses to coprocessor primary register CRn = 0 to Hyp mode.

The reset value is 0.

To access the HSTR:

MRC p15, 4, <Rt>, c1, c1, 3 ; Read HSTR into Rt
MCR p15, 4, <Rt>, c1, c1, 3 ; Write Rt to HSTR

Register access is encoded as follows:

Table B1-53 HSTR access encoding

coproc opc1 CRn CRm opc2
1111 100 0001 0001 011
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