|Non-Confidential||PDF version||ARM 100241_0001_00_en|
|Home > Register Descriptions > AArch32 system registers > DFSR with Long-descriptor translation table format|
DFSR has a specific format when using the Long-descriptor translation table format.
The following figure shows the DFSR bit assignments when using the Long-descriptor translation table format.
Cache maintenance fault. For synchronous faults, this bit indicates whether a cache maintenance operation generated the fault:
|Abort not caused by a cache maintenance operation.|
|Abort caused by a cache maintenance operation.|
External abort type. This field indicates whether an AXI Decode or Slave error caused an abort:
|External abort marked as DECERR.|
|External abort marked as SLVERR.|
For aborts other than external aborts this bit always returns 0.
Write not Read bit. This field indicates whether the abort was caused by a write or a read access:
|Abort caused by a read access.|
|Abort caused by a write access.|
For faults on CP15 cache maintenance operations, including the VA to PA translation operations, this bit always returns a value of 1.
Fault Status bits. This field indicates the type of exception generated. Any encoding not listed is reserved.
|Address size fault in TTBR0 or TTBR1.|
|Translation fault, LL bits indicate level.|
|Access fault flag, LL bits indicate level.|
|Permission fault, LL bits indicate level.|
|Synchronous external abort.|
|Asynchronous external abort.|
|Synchronous external abort on translation table walk, LL bits indicate level.|
|Synchronous parity error on memory access.|
|Asynchronous parity error on memory access (DFSR only).|
|Synchronous parity error on memory access on translation table walk, first level, LL bits indicate level.|
|TLB conflict abort.|
Table B1-43 Encodings of LL bits associated with the MMU fault
To access the DFSR:
MRC p15, 0, <Rt>, c5, c0, 0; Read DFSR into Rt MCR p15, 0, <Rt>, c5, c0, 0; Write Rt to DFSR