B1.51 DFSR with Long-descriptor translation table format

DFSR has a specific format when using the Long-descriptor translation table format.

The following figure shows the DFSR bit assignments when using the Long-descriptor translation table format.

Figure B1-14 DFSR bit assignments for Long-descriptor translation table format
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

Reserved, res0.
CM, [13]

Cache maintenance fault. For synchronous faults, this bit indicates whether a cache maintenance operation generated the fault:

0Abort not caused by a cache maintenance operation.
1Abort caused by a cache maintenance operation.
ExT, [12]

External abort type. This field indicates whether an AXI Decode or Slave error caused an abort:

0External abort marked as DECERR.
1External abort marked as SLVERR.

For aborts other than external aborts this bit always returns 0.

WnR, [11]

Write not Read bit. This field indicates whether the abort was caused by a write or a read access:

0Abort caused by a read access.
1Abort caused by a write access.

For faults on CP15 cache maintenance operations, including the VA to PA translation operations, this bit always returns a value of 1.

Reserved, res0.
Reserved, res0.
Status, [5:0]

Fault Status bits. This field indicates the type of exception generated. Any encoding not listed is reserved.

0b000000Address size fault in TTBR0 or TTBR1.
0b0001LLTranslation fault, LL bits indicate level.
0b0010LLAccess fault flag, LL bits indicate level.
0b0011LLPermission fault, LL bits indicate level.
0b010000Synchronous external abort.
0b010001Asynchronous external abort.
0b0101LLSynchronous external abort on translation table walk, LL bits indicate level.
0b011000Synchronous parity error on memory access.
0b011001Asynchronous parity error on memory access (DFSR only).
0b0111LLSynchronous parity error on memory access on translation table walk, first level, LL bits indicate level.
0b100001Alignment fault.
0b100010Debug event.
0b110000TLB conflict abort.
0b110101LDREX or STREX abort.

Table B1-43 Encodings of LL bits associated with the MMU fault

Bits Meaning
0b00 Reserved
0b01 Level 1
0b10 Level 2
0b11 Level 3

To access the DFSR:

MRC p15, 0, <Rt>, c5, c0, 0; Read DFSR into Rt
MCR p15, 0, <Rt>, c5, c0, 0; Write Rt to DFSR
Non-ConfidentialPDF file icon PDF versionARM 100241_0001_00_en
Copyright © 2016, 2017 ARM Limited or its affiliates. All rights reserved.