B1.89 IFSR with Long-descriptor translation table format

IFSR has a specific format when using the Long-descriptor translation table format.

The following figure shows the IFSR bit assignments when using the Long-descriptor translation table format.

Figure B1-43 IFSR bit assignments for Long-descriptor translation table format
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


[31:13]
Reserved, res0.
ExT,[12]

External abort type. This field indicates whether an AXI Decode or Slave error caused an abort:

0External abort marked as DECERR.
1External abort marked as SLVERR.

For aborts other than external aborts this bit always returns 0.

[11:10]
Reserved, res0.
[9]
RAO.
[8:6]
Reserved, res0.
Status,[5:0]

Fault Status bits. This field indicates the type of exception generated. Any encoding not listed is reserved.

0b000000Address size fault in TTBR0 or TTBR1.
0b0001LLTranslation fault, LL bits indicate level.
0b0010LLAccess fault flag, LL bits indicate level.
0b0011LLPermission fault, LL bits indicate level.
0b010000Synchronous external abort.
0b0101LLSynchronous external abort on translation table walk, LL bits indicate level.
0b011000Synchronous parity error on memory access.
0b0111LLSynchronous parity error on memory access on translation table walk, LL bits indicate level.
0b100001Alignment fault.
0b100010Debug event.
0b110000TLB conflict abort.

Table B1-69 Encodings of LL bits associated with the MMU fault

Bits Meaning
0b00 Reserved
0b01 Level 1
0b10 Level 2
0b11 Level 3

If a Data Abort exception is generated by an instruction cache maintenance operation when the Long-descriptor translation table format is selected, the fault is reported as a Cache Maintenance fault in the DFSR or HSR with the appropriate Fault Status code. For such exceptions reported in the DFSR, the corresponding IFSR is unknown.

To access the IFSR:

MRC p15, 0, <Rt>, c5, c0, 1; Read IFSR into Rt
MCR p15, 0, <Rt>, c5, c0, 1; Write Rt to IFSR

Register access is encoded as follows:

Table B1-70 IFSR access encoding

coproc opc1 CRn CRm opc2
1111 000 0101 0000 001
Non-ConfidentialPDF file icon PDF versionARM 100241_0001_00_en
Copyright © 2016, 2017 ARM Limited or its affiliates. All rights reserved.