B1.68 Hyp Syndrome Register

The HSR characteristics are:

Purpose
Holds syndrome information for an exception taken to Hyp mode.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - - RW RW -
Configurations

This register is accessible only at EL2 or EL3.

Attributes
HSR is a 32-bit register.
Figure B1-24 HSR bit assignments
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EC, [31:26]

Exception class. The exception class for the exception that is taken in Hyp mode. See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information.

IL, [25]

Instruction length. See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information.

ISS, [24:0]

Instruction specific syndrome. See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information. The interpretation of this field depends on the value of the EC field. See B1.52 Encoding of ISS[24:20] when HSR[31:30] is 0b00.

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