B1.86 Instruction Fault Address Register

The IFAR characteristics are:

Purpose
Holds the virtual address of the faulting address that caused a synchronous Prefetch Abort exception.
Usage constraints

This register is accessible as follows:

 

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

IFAR(S) - - - RW - - RW
IFAR(NS) - - RW - RW RW -
Configurations

There are separate Secure and Non-secure instances of this register at EL3.

IFAR (S) is architecturally mapped to HIFAR. See B1.65 Hyp Instruction Fault Address Register.

Attributes
IFAR is a 32-bit register.
Figure B1-41 IFAR bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


VA, [31:0]

The Virtual Address of faulting address of synchronous Prefetch Abort exception.

To access the IFAR:

MRC p15, 0, <Rt>, c6, c0, 2; Read IFAR into Rt
MCR p15, 0, <Rt>, c6, c0, 2; Write Rt to IFAR
Non-ConfidentialPDF file icon PDF versionARM 100241_0001_00_en
Copyright © 2016, 2017 ARM Limited or its affiliates. All rights reserved.