B1.65 Hyp Instruction Fault Address Register

The HIFAR characteristics are:

Purpose
Holds the virtual address of the faulting address that caused a synchronous Prefetch Abort exception that is taken to Hyp mode.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - - RW RW -

Execution in any Non-secure mode other than Hyp mode makes HPFAR unknown.

Configurations

HIFAR is architecturally mapped to IFAR (S). See B1.86 Instruction Fault Address Register.

Attributes
HIFAR is a 32-bit register.
Figure B1-21 HIFAR bit assignments
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VA, [31:0]

The Virtual Address of faulting address of synchronous Prefetch Abort exception.

To access the HIFAR:

MRC p15, 4, <Rt>, c6, c0, 2 ; Read HIFAR into Rt
MCR p15, 4, <Rt>, c6, c0, 2 ; Write Rt to HIFAR

Register access is encoded as follows:

Table B1-50 HIFAR access encoding

coproc opc1 CRn CRm opc2
1111 100 0110 0000 010
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