B1.92 L2 Control Register

The L2CTLR characteristics are:

Purpose
Provides implementation defined control options for the L2 memory system.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RW RW RW RW RW

L2CTLR is writable. However, all writes to this register are ignored.

Configurations

There is one L2CTLR for the Cortex®‑A32 processor.

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes
L2CTLR is a 32-bit register.
Figure B1-46 L2CTLR bit assignments
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[31:26]

Reserved, res0.

Number of cores, [25:24]

Number of cores present:

0b00One core, core 0.
0b01Two cores, core 0 and core 1.
0b10Three cores, cores 0 to 2.
0b11Four cores, cores 0 to 3.

These bits are read-only and the value of this field is set to the number of cores present in the configuration.

[23]
Reserved, RAZ.
CPU Cache Protection, [22]

CPU Cache Protection. Core RAMs are implemented:

0Without ECC.
1With ECC.

This field is RO.

SCU-L2 Cache Protection, [21]

SCU-L2 Cache Protection. L2 cache is implemented:

0Without ECC.
1With ECC.

This field is RO.

[20:6]

Reserved, RAZ.

L2 Data RAM input latency, [5]

L2 data RAM input latency

01-cycle input delay from L2 data RAMs.
12-cycle input delay from L2 data RAMs.

This field is RO.

[4:1]
Reserved, RAZ.
L2 Data RAM output latency, [0]

L2 data RAM output latency:

02-cycle output delay from L2 data RAMs.
13-cycle output delay from L2 data RAMs.

This field is RO.

To access the L2CTLR:

MRC p15, 1, <Rt>, c9, c0, 2; Read L2CTLR into Rt

Register access is encoded as follows:

Table B1-73 L2CTLR access encoding

coproc opc1 CRn CRm opc2
1111 001 1001 0000 010
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