B1.101 Primary Region Remap Register

The PRRR characteristics are:

Purpose
Controls the top level mapping of the TEX[0], C, and B memory region attributes.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RW RW RW RW RW

PRRR is not accessible when the Long-descriptor translation table format is in use. See, instead, B1.95 Memory Attribute Indirection Registers 0 and 1.

Configurations

There are separate Secure and Non-secure instances of this register at EL3.

Attributes
PRRR is a 32-bit register when TTBCR.EAE==0.
Figure B1-54 PRRR bit assignments
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NOSn, [24+n]

Outer Shareable property mapping for memory attributes n, where n is 0-7, if the region is mapped as Normal Shareable. n is the value of the TEX[0], C and B bits concatenated. The possible values of each NOSn bit are:

0Memory region is Outer Shareable.
1Memory region is Inner Shareable.

The value of this bit is ignored if the region is Normal or Device memory that is not Shareable.

[23:20]
Reserved, res0.
NS1, [19]

Mapping of S = 1 attribute for Normal memory. This bit gives the mapped Shareable attribute for a region of memory that:

  • Is mapped as Normal memory.
  • Has the S bit set to 1.

The possible values of the bit are:

0Region is not Shareable.
1Region is Shareable.
NS0, [18]

Mapping of S = 0 attribute for Normal memory. This bit gives the mapped Shareable attribute for a region of memory that:

  • Is mapped as Normal memory.
  • Has the S bit set to 0.

The possible values of the bit are the same as those given for the NS1 bit, bit[19].

DS1, [17]

Mapping of S = 1 attribute for Device memory. This bit gives the mapped Shareable attribute for a region of memory that:

  • Is mapped as Device memory.
  • Has the S bit set to 1.

This field has no significance in the processor.

DS0, [16]

Mapping of S = 0 attribute for Device memory. This bit gives the mapped Shareable attribute for a region of memory that:

  • Is mapped as Device memory.
  • Has the S bit set to 0.

This field has no significance in the processor.

TRn, [2n+1:2n]

Primary TEX mapping for memory attributes n, where n is 0-7. n is the value of the TEX[0], C and B bits, see Memory attributes and the n value for the PRRR field descriptions. This field defines the mapped memory type for a region with attributes n. The possible values of the field are:

0b00Device (nGnRnE).
0b01Device (not nGnRnE).
0b10Normal Memory.
0b11Reserved, effect is unpredictable.

The following table shows the mapping between the memory region attributes and the n value used in the PRRR.nOSn and PRRR.TRn field descriptions.

Table B1-85 Memory attributes and the n value for the PRRR field descriptions

Attributes n value
TEX[0] C B
0 0 0 0
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 6
1 1 1 7

Large physical address translations use Long-descriptor translation table formats and MAIR0 replaces the PRRR, and MAIR1 replaces the NMRR. For more information see B1.95 Memory Attribute Indirection Registers 0 and 1.

To access the PRRR:

MRC p15, 0, <Rt>, c10, c2, 0    ; Read PRRR into Rt
MCR p15, 0, <Rt>, c10, c2, 0    ; Write Rt to PRRR

Register access is encoded as follows:

Table B1-86 PRRR access encoding

coproc opc1 CRn CRm opc2
1111 000 1010 0010 000
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