B1.95 Memory Attribute Indirection Registers 0 and 1

The MAIR0 and MAIR1 characteristics are:

Purpose
To provide the memory attribute encodings corresponding to the possible AttrIndx values in a Long-descriptor format translation table entry for stage 1 translations.
Usage constraints

These registers are accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RW RW RW RW RW

Accessible only when using the Long-descriptor translation table format. When using the Short-descriptor format see, instead, B1.101 Primary Region Remap Register and B1.99 Normal Memory Remap Register.

AttrIndx[2], from the translation table descriptor, selects the appropriate MAIR: setting AttrIndx[2] to 0 selects MAIR0.

The Secure instance of the register gives the value for memory accesses from Secure state.

The Non-secure instance of the register gives the value for memory accesses from Non-secure states other than Hyp mode.

Configurations

There are separate Secure and Non-secure instances of this register at EL3.

Attributes
MAIR0 is a 32-bit register when TTBCR.EAE==1.
Figure B1-49 MAIR0 and MAIR1 bit assignments
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Attrm, [7:0]

Where m is 0-7.

The memory attribute encoding for an AttrIndx[2:0] entry in a Long descriptor format translation table entry, where:

  • AttrIndx[2] selects the appropriate MAIR:

    • Setting AttrIndx[2] to 0 selects MAIR0.

    • Setting AttrIndx[2] to 1 selects MAIR1.
  • AttrIndx[2:0] gives the value of <n> in Attr<n>.

Table B1-76 Attr<n>[7:4] bit assignments

Bits Meaning
0b0000 Device memory. See Attr<n>[3:0] bit assignments for the type of Device memory.
0b00RW, RW not 00

Normal Memory, Outer Write-through transient.

The transient hint is ignored.

0b0100 Normal Memory, Outer Non-Cacheable.
0b01RW, RW not 00

Normal Memory, Outer Write-back transient.

The transient hint is ignored.

0b10RW Normal Memory, Outer Write-through non-transient.
0b11RW Normal Memory, Outer Write-back non-transient.

The following table shows the Attr<n>[3:0] bit assignments. The encoding of Attr<n>[3:0] depends on the value of Attr<n>[7:4].

Table B1-77 Attr<n>[3:0] bit assignments

Bits Meaning when Attr<n>[7:4] is 0000 Meaning when Attr<n>[7:4] is not 0000
0b0000 Device-nGnRnE memory unpredictable
0b00RW, RW not 00 unpredictable Normal Memory, Inner Write-through transient
0b0100 Device-nGnRE memory Normal memory, Inner Non-Cacheable
0b01RW, RW not 00 unpredictable Normal Memory, Inner Write-back transient
0b1000 Device-nGRE memory Normal Memory, Inner Write-through non-transient (RW=00)
0b10RW, RW not 00 unpredictable Normal Memory, Inner Write-through non-transient
0b1100 Device-GRE memory Normal Memory, Inner Write-back non-transient (RW=00)
0b11RW, RW not 00 unpredictable Normal Memory, Inner Write-back non-transient

The following table shows the encoding of the R and W bits that are used, in some Attr<n> encodings in Table B1-76 Attr<n>[7:4] bit assignments and Table B1-77 Attr<n>[3:0] bit assignments, to define the read-allocate and write-allocate policies:

Table B1-78 Encoding of R and W bits in some Attrm fields

R or W Meaning
0 Do not allocate
1 Allocate

To access the MAIR0:

MRC p15, 0, <Rt>, c10, c2, 0    ; Read MAIR0 into Rt
MCR p15, 0, <Rt>, c10, c2, 0    ; Write Rt to MAIR0

Register access is encoded as follows:

Table B1-79 MAIR0 access encoding

coproc opc1 CRn CRm opc2
1111 000 1010 0010 000

To access the MAIR1:

MRC p15, 0, <Rt>, c10, c2, 1    ; Read MAIR1 into Rt
MCR p15, 0, <Rt>, c10, c2, 1    ; Write Rt to MAIR1

Register access is encoded as follows:

Table B1-80 MAIR1 access encoding

coproc opc1 CRn CRm opc2
1111 000 1010 0010 001
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