B1.119 Vector Base Address Register

The VBAR characteristics are:

Purpose
Holds the exception base address for exceptions that are not taken to Monitor mode or to Hyp mode when high exception vectors are not selected.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RW RW RW RW RW

Software must program the Non-secure instance of the register with the required initial value as part of the processor boot sequence.

Configurations

There are separate Secure and Non-secure instances of this register at EL3.

Attributes
VBAR is a 32-bit register.
Figure B1-67 VBAR bit assignments
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Vector Base Address, [31:5]
Bits[31:5] of the base address of the exception vectors, for exceptions taken in this exception level. Bits[4:0] of an exception vector are the exception offset.
[4:0]
Reserved, res0.

To access the VBAR:

MRC p15, 0, <Rt>, c12, c0, 0 ; Read VBAR into Rt
MCR p15, 0, <Rt>, c12, c0, 0 ; Write Rt to VBAR

Register access is encoded as follows:

Table B1-98 VBAR access encoding

coproc opc1 CRn CRm opc2
1111 000 1100 0000 000
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