B1.103 Reset Management Register

The RMR characteristics are:

Purpose
Controls the execution state that the processor boots into and allows request of a warm reset.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - - - RW RW
Configurations

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes
RMR is a 32-bit register.
Figure B1-56 RMR bit assignments
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[31:2]

Reserved, res0.

RR, [1]

Reset Request. The possible values are:

0This is the reset value.
1Requests a warm reset. This bit is set to 0 by either a cold or warm reset.

The bit is strictly a request.

The RR bit drives the WARMRSTREQ output signal.

AA64, [0]

Reserved, res0.

To access the RMR:

MRC p15,0,<Rt>,c12,c0,2 ; Read RMR into Rt
MCR p15,0,<Rt>,c12,c0,2 ; Write Rt to RMR

Register access is encoded as follows:

Table B1-88 RMR access encoding

coproc opc1 CRn CRm opc2
1111 000 1100 0000 010
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