B1.91 L2 Auxiliary Control Register

The L2ACTLR characteristics are:

Purpose
Provides configuration and control options for the L2 memory system.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RW RW RW RW RW

You can write to this register only when the L2 memory system is idle. ARM recommends that you write to this register after a powerup reset before the MMU is enabled and before any AXI, ACE, CHI, or ACP traffic has begun.

If the register must be modified after a powerup reset sequence, to idle the L2 memory system, you must take the following steps:

  1. Disable the MMU from each core followed by an ISB to ensure the MMU disable operation is complete, then followed by a DSB to drain previous memory transactions.
  2. Ensure that the system has no outstanding AC channel coherence requests to the Cortex®‑A32 processor.
  3. Ensure that the system has no outstanding ACP requests to the Cortex‑A32 processor.

When the L2 is idle, the processor can update the L2ACTLR followed by an ISB. After the L2ACTLR is updated, the MMUs can be enabled and normal ACE and ACP traffic can resume.

Configurations

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes
L2ACTLR is a 32-bit register.
Figure B1-45 L2ACTLR bit assignments
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[31:30]

L2 Victim Control.

0b10This is the default value. Software must not change it.
L2DEIEN, [29]

L2 cache data RAM error injection enable. The possible values are:

0Normal behavior, errors are not injected. This is the reset value.
1Double-bit errors are injected on all writes to the L2 cache data RAMs.
[28:25]

Reserved, res0.

L2TEIEN, [24]

L2 cache tag RAM error injection enable. The possible values are:

0Normal behavior, errors are not injected. This is the reset value.
1Double-bit errors are injected on all writes to the L2 cache tag RAMs.
[23:15]

Reserved, res0.

Enable UniqueClean evictions with data, [14]

Enables UniqueClean evictions with data. The possible values are:

0Disables UniqueClean evictions with data. This is the reset value for ACE.
1Enables UniqueClean evictions with data. This is the reset value for CHI.

In AXI implementations, this field is res0.

[13:4]

Reserved, res0.

Disable clean/evict push to external, [3]

Disables clean/evict push to external. The possible values are:

0Enables clean/evict to be pushed out to external. This is the reset value for ACE.
1Disables clean/evict from being pushed to external. This is the reset value for CHI.

In AXI implementations, this field is res1.

[2:0]

Reserved, res0.

To access the L2ACTLR:

MRC p15, 1, <Rt>, c15, c0, 0; Read L2ACTLR into Rt
MCR p15, 1, <Rt>, c15, c0, 0; Write Rt to L2ACTLR

Register access is encoded as follows:

Table B1-72 L2ACTLR access encoding

coproc opc1 CRn CRm opc2
1111 001 1111 0000 000
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