B1.42 CPU Auxiliary Control Register

The CPUACTLR characteristics are:

Purpose
Provides implementation defined configuration and control options for the processor. There is one 64-bit CPU Auxiliary Control Register for each core in the processor.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RW RW RW RW RW

The CPU Auxiliary Control Register can be written only when the system is idle. ARM recommends that you write to this register after a powerup reset, before the MMU is enabled, and before any master interface or ACP traffic begins.

Setting many of these bits can cause significantly lower performance on your code. Therefore, it is suggested that you do not modify this register unless directed by ARM.

Configurations

CPUACTLR is common to the Secure and Non-secure states.

Attributes

CPUACTLR is a 64-bit register.

Figure B1-6 CPUACTLR bit assignments
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[63:45]
Reserved, res0.
ENDCCASCI, [44]

Enable data cache clean as data cache clean/invalidate. The possible values are:

0Normal behavior, data cache clean operations are unaffected. This is the reset value.
1

Executes data cache clean operations as data cache clean and invalidate. The following operations are affected:

  • DCCSW is executed as DCCISW, DCCMVAU and DCCMVAC are executed as DCCIMVAC.
[43:31]
Reserved, res0.
CDIDIS, [30]

Disable Cryptographic dual issue. The possible values are:

0

Enable dual issue of Advanced SIMD and Cryptographic instructions. This is the reset value.

1Disable dual issue of Advanced SIMD and Cryptographic instructions.
DIDIS, [29]

Disable Dual Issue. The possible values are:

0Enable Dual Issue of instructions. This is the reset value.
1Disable Dual Issue of all instructions.
RADIS, [28:27]

Write streaming no-allocate threshold. The possible values are:

0b0016th consecutive streaming cache line does not allocate in the L1 or L2 cache.
0b01128th consecutive streaming cache line does not allocate in the L1 or L2 cache. This is the reset value.
0b10512th consecutive streaming cache line does not allocate in the L1 or L2 cache.
0b11Disables streaming. All write-allocate lines allocate in the L1 or L2 cache.
L1RADIS, [26:25]

Write streaming no-L1-allocate threshold. The possible values are:

0b004th consecutive streaming cache line does not allocate in the L1 cache. This is the reset value.
0b0164th consecutive streaming cache line does not allocate in the L1 cache.
0b10128th consecutive streaming cache line does not allocate in the L1 cache.
0b11Disables streaming. All write-allocate lines allocate in the L1 cache.
DTAH, [24]

Disable transient and no-read-allocate hints for loads. The possible values are:

0Normal operation.
1Transient and no-read-allocate hints in the MAIR are ignored and treated the same as non-transient, read-allocate types for loads. This is the reset value.
STBPFRS, [23]

Disable ReadUnique request for prefetch streams initiated by STB accesses:

0ReadUnique used for prefetch streams initiated from STB accesses. This is the reset value.
1ReadShared used for prefetch streams initiated from STB accesses.
STBPFDIS, [22]

Disable prefetch streams initiated from STB accesses:

0Enable Prefetch streams initiated from STB accesses. This is the reset value.
1Disable Prefetch streams initiated from STB accesses.
[21]
Reserved, res0.
NPFSTRM, [20:19]

Number of independent data prefetch streams. The possible values are:

0b001 stream.
0b012 streams. This is the reset value.
0b103 streams.
0b114 streams.
DSTDIS, [18]

Enable device split throttle. The possible values are:

0Device split throttle disabled.
1Device split throttle enabled. This is the reset value.
STRIDE, [17]

Enable stride detection. The possible values are:

02 consecutive strides to trigger prefetch. This is the reset value.
13 consecutive strides to trigger prefetch.
[16]
Reserved, res0.
L1PCTL, [15:13]

L1 Data prefetch control. The value of the this field determines the maximum number of outstanding data prefetches allowed in the L1 memory system, excluding those generated by software load or PLD instructions. The possible values are:

0b000Prefetch disabled.
0b0011 outstanding prefetch allowed.
0b0102 outstanding prefetches allowed.
0b0113 outstanding prefetches allowed.
0b1004 outstanding prefetches allowed.
0b1015 outstanding prefetches allowed. This is the reset value.
0b1106 outstanding prefetches allowed.
0b1118 outstanding prefetches allowed.
[12]
Reserved, res0.
DYNSDIS, [11]

Disable dynamic stride adjustment for prefetch streams. The possible values are:

0Enable dynamic stride adjustment. This is the reset value.
1Disable dynamic stride adjustment.
DODMBS, [10]

Disable optimized Data Memory Barrier behavior. The possible values are:

0Enable optimized Data Memory Barrier behavior. This is the reset value.
1Disable optimized Data Memory Barrier behavior.
[9:7]
Reserved, res0.
L1DEIEN, [6]

L1 D-cache data RAM error injection enable. The possible values are;

0Normal behavior, errors are not injected. This is the reset value.
1Double-bit errors are injected on all writes to the L1 D-cache data RAMs for the first word of each 32-byte region.
[5:0]
Reserved, res0.

To access the CPUACTLR:

MRRC p15, 0, <Rt>, <Rt2>, c15; Read CPU Auxiliary Control Register
MCRR p15, 0, <Rt>, <Rt2>, c15; Write CPU Auxiliary Control Register

Register access is encoded as follows:

Table B1-36 CPUACTLR access encoding

coproc opc1 CRm
1111 0000 1111
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