B1.43 CPU Extended Control Register

The CPUECTLR characteristics are:

Purpose
Provides additional implementation defined configuration and control options for the processor.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RW RW RW RW RW

The CPUECTLR can be written dynamically.

Configurations
There are no configuration notes.
Attributes

CPUECTLR is a 64-bit register.

Figure B1-7 CPUECTLR bit assignments
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[63:7]

Reserved, res0.

SMPEN, [6]

Enable hardware management of data coherency with other cores in the cluster. The possible values are:

0Disables data coherency with other cores in the cluster. This is the reset value.
1Enables data coherency with other cores in the cluster.

Set the SMPEN bit before enabling the caches, even if there is only one core in the system.

FPRETCTL, [5:3]

Advanced SIMD and floating-point retention control. The possible values are:

0b000Disable the retention circuit. This is the reset value.
0b0012 Architectural Timer ticks are required before retention entry.
0b0108 Architectural Timer ticks are required before retention entry.
0b01132 Architectural Timer ticks are required before retention entry.
0b10064 Architectural Timer ticks are required before retention entry.
0b101128 Architectural Timer ticks are required before retention entry.
0b110256 Architectural Timer ticks are required before retention entry.
0b111512 Architectural Timer ticks are required before retention entry.

This field is present only if the Advanced SIMD and floating-point support is implemented. Otherwise, it is res0.

CPURETCTL, [2:0]

CPU retention control. The possible values are:

0b000Disable the retention circuit. This is the reset value.
0b0012 Architectural Timer ticks are required before retention entry.
0b0108 Architectural Timer ticks are required before retention entry.
0b01132 Architectural Timer ticks are required before retention entry.
0b10064 Architectural Timer ticks are required before retention entry.
0b101128 Architectural Timer ticks are required before retention entry.
0b110256 Architectural Timer ticks are required before retention entry.
0b111512 Architectural Timer ticks are required before retention entry.

To access the CPUECTLR:

MRRC p15, 1, <Rt>, <Rt2>, c15; Read CPU Extended Control Register
MCRR p15, 1, <Rt>, <Rt2>, c15; Write CPU Extended Control Register

Register access is encoded as follows:

Table B1-37 CPUECTLR access encoding

coproc opc1 CRm
1111 0001 1111
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