B1.44 CPU Memory Error Syndrome Register

The CPUMERRSR characteristics are:

Purpose

Holds ECC errors on the:

  • L1 data RAMs.
  • L1 tag RAMs.
  • TLB RAMs.

This register is used for recording ECC errors on all processor RAMs.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RW RW RW RW RW
Configurations

There is one copy of this register that is used in both Secure and Non-secure states.

A write of any value to the register updates the register to 0000000000000000.

Attributes

CPUMERRSR is a 64-bit register.

Figure B1-8 CPUMERRSR bit assignments
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Fatal, [63]

Fatal bit. This bit is set to 1 on the first memory error that caused a data abort. It is a sticky bit so that after it is set, it remains set until the register is written.

The reset value is 0.

[62:48]

Reserved, res0.

Other error count, [47:40]

This field is set to 0 on the first memory error and is incremented on any memory error that does not match the RAMID and Bank/Way information in this register while the sticky Valid bit is set.

The reset value is 0.

Repeat error count, [39:32]

This field is set to 0 on the first memory error and is incremented on any memory error that exactly matches the RAMID and Bank/Way information in this register while the sticky Valid bit is set.

The reset value is 0.

Valid, [31]

Valid bit. This bit is set to 1 on the first memory error. It is a sticky bit so that after it is set, it remains set until the register is written.

The reset value is 0.

RAMID, [30:24]

RAM Identifier. Indicates the RAM in which the first memory error. The possible values are:

0x00L1 Instruction tag RAM.
0x01L1 Instruction data RAM.
0x08L1 Data tag RAM.
0x09L1 Data data RAM.
0x0AL1 Data dirty RAM.
0x18TLB RAM.
[23:21]

Reserved, res0.

CPUID/Way, [20:18]

Indicates the RAM where the first memory error occurred.

L1 I-tag RAM
0x0Way 0
0x1Way 1
0x2-0x7Unused
L1 I-data RAM
0x0Bank 0
0x1Bank 1
0x2-0x7Unused
TLB RAM
0x0Way 0
0x1Way 1
0x2-0x7Unused
L1 D-dirty RAM
0x0Dirty RAM
0x1-0x7Unused
L1 D-tag RAM
0x0Way 0
0x1Way 1
0x2Way 2
0x3Way 3
0x4-0x7Unused
L1 D-data RAM
0x0Way0-Bank0
0x1Way0-Bank1
0x2Way1-Bank0
0x3Way1-Bank1
...
0x7Way3-Bank1
[17:12]

Reserved, res0.

RAM address, [11:0]

Indicates the index address of the first memory error.

  • A fatal error results in the RAMID, Way, and RAM address recording the fatal error, even if the sticky bit is set.
  • Only L1 Data data and L1 Data dirty RAMs can signal fatal errors, because all other RAM instances are protected only by parity.
  • If two or more memory errors in the same RAM occur in the same cycle, only one error is reported.
  • If two or more first memory error events from different RAMs occur in the same cycle, one of the errors is selected arbitrarily.
  • If two or more memory error events from different RAMs, that do not match the RAMID, Way, and index information in this register while the sticky Valid bit is set, occur in the same cycle, then the Other error count field is incremented only by one.

To access the CPUMERRSR:

MRRC p15, 2, <Rt>, <Rt2>, c15;  Read CPUMERRSR into Rt and Rt2
MCRR p15, 2, <Rt>, <Rt2>, c15;  Write Rt and Rt2 to CPUMERRSR

Register access is encoded as follows:

Table B1-38 CPUMERRSR access encoding

coproc opc1 CRm
1111 0010 1111
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