B1.94 L2 Memory Error Syndrome Register

The L2MERRSR characteristics are:

Purpose

Holds ECC errors on the:

  • L2 data RAMs.
  • L2 tag RAMs.
  • SCU snoop filter RAMs.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RW RW RW RW RW
Configurations

There is one copy of this register that is used in both Secure and Non-secure states.

A write of any value to the register updates the register to 0x0000000000000000.

Attributes

L2MERRSR is a a 64-bit register.

Figure B1-48 L2MERRSR bit assignments
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Fatal, [63]

Fatal bit. This bit is set to 1 on the first memory error that caused a data abort. It is a sticky bit so that after it is set, it remains set until the register is written.

The reset value is 0.

[62:48]

Reserved, res0.

Other error count, [47:40]

This field is set to 0 on the first memory error and is incremented on any memory error that does not match the RAMID and Bank/Way information in this register while the sticky Valid bit is set.

The reset value is 0.

Repeat error count, [39:32]

This field is set to 0 on the first memory error and is incremented on any memory error that exactly matches the RAMID and Bank/Way information in this register while the sticky Valid bit is set.

The reset value is 0.

Valid, [31]

Valid bit. This bit is set to 1 on the first memory error. It is a sticky bit so that after it is set, it remains set until the register is written.

The reset value is 0.

RAMID, [30:24]

RAM Identifier. Indicates the RAM in which the first memory error occurred. The possible values are:

0x10L2 tag RAM.
0x11L2 data RAM.
0x12SCU snoop filter RAM.
[23:22]

Reserved, res0.

CPUID/Way, [21:18]

Indicates the RAM where the first memory error occurred.

L2 tag RAM
0x0Way 0
0x1Way 1
...
0x6Way 6
0x7Way 7
L2 data RAM
0x0Bank 0
0x1Bank 1
...
0x7Bank 7
0x8-0xFUnused
SCU snoop filter RAM
0x0CPU0:Way0
0x1CPU0:Way1
...
0xECPU3:Way2
0xFCPU3:Way3
[17]

Reserved, res0.

RAM Address, [16:3]

Indicates the index address of the first memory error.

[2:0]

Reserved, res0.

  • A fatal error results in the RAMID, CPU ID/Way and RAM address recording the fatal error, even if the sticky bit was set.
  • If two or more memory errors in the same RAM occur in the same cycle, only one error is reported.
  • If two or more first memory error events from different RAMs occur in the same cycle, one of the errors is selected arbitrarily, while the Other error count field is incremented only by one.
  • If two or more memory error events from different RAMs, that do not match the RAMID, bank, way, or index information in this register while the sticky Valid bit is set, occur in the same cycle, the Other error count field is incremented only by one.

To access the L2MERRSR:

MRRC p15, 3, <Rt>, <Rt2>, c15;  Read L2MERRSR into Rt and Rt2
MCRR p15, 3, <Rt>, <Rt2>, c15;  Write Rt and Rt2 to L2MERRSR

Register access is encoded as follows:

Table B1-75 L2MERRSR access encoding

coproc opc1 CRm
1111 0011 1111
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