C6.4 Debug ID Register

The DBGDIDR characteristics are:

Purpose

Specifies:

  • The version of the Debug architecture that is implemented.
  • Some features of the debug implementation.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

RO RO RO RO RO RO RO
Configurations

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes
See C6.1 AArch32 debug register summary.
Figure C6-3 DBGDIDR bit assignments
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WRPs, [31:28]

The number of Watchpoint Register Pairs (WRPs) implemented. The number of implemented WRPs is one more than the value of this field. The value is:

0x3The processor implements 4 WRPs.
BRPs, [27:24]

The number of Breakpoint Register Pairs (BRPs) implemented. The number of implemented BRPs is one more than the value of this field. The value is:

0x5The processor implements 6 BRPs.
CTX_CMPs, [23:20]

The number of BRPs that can be used for Context matching. This is one more than the value of this field. The value is:

0x1The processor implements two Context matching breakpoints, breakpoints 4 and 5.
Version, [19:16]

The Debug architecture version.

0x6The processor implements ARMv8 Debug architecture.
DEVID_imp, [15]

Reserved, RAO.

nSUHD_imp, [14]

Secure User Halting Debug not implemented bit. The value is:

1The processor does not implement Secure User Halting Debug.
PCSR_imp, [13]
Reserved, RAZ.
SE, [12]

EL3 implemented. The value is:

1The processor implements EL3.
[11:0]

Reserved, res0.

To access the DBGDIDR:

MRC p14, 0, <Rt>, c0, c0, 0; Read Debug ID Register
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