C6.5 Debug Device ID Register

The DBGDEVID characteristics are:

Purpose
Specifies the version of the Debug architecture is implemented, and some features of the debug implementation.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RO RO RO RO RO
Configurations

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes
See C6.1 AArch32 debug register summary.
Figure C6-4 DBGDEVID bit assignments
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CIDMask, [31:28]

Specifies the level of support for the Context ID matching breakpoint masking capability. This value is:

0x0Context ID masking is not implemented.
AuxRegs, [27:24]

Specifies support for the Debug External Auxiliary Control Register. This value is:

0x0None supported.
DoubleLock, [23:20]

Specifies support for the Debug OS Double Lock Register. This value is:

0x1The processor supports Debug OS Double Lock Register.
VirtExtns, [19:16]

Specifies whether EL2 is implemented. This value is:

0x1The processor implements EL2.
VectorCatch, [15:12]

Defines the form of the vector catch event implemented. This value is:

0x0The processor implements address matching form of vector catch.
BPAddrMask, [11:8]

Indicates the level of support for the Immediate Virtual Address (IVA) matching breakpoint masking capability. This value is:

0xFBreakpoint address masking not implemented. DBGBCRn[28:24] are res0.
WPAddrMask, [7:4]

Indicates the level of support for the DVA matching watchpoint masking capability. This value is:

0x1Watchpoint address mask implemented.
PCSample, [3:0]

Indicates the level of support for Program Counter sampling using debug registers 40 and 41. This value is:

0x3EDPCSR, EDCIDSR and EDVIDSR are implemented as debug registers 40, 41, and 42.

To access the DBGDEVID:

MRC p14, 0, <Rt>, c7, c2, 7; Read Debug Device ID Register 0
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