C7.2 External Debug Reserve Control Register

The EDRCR characteristics are:

Purpose

This register is used to allow imprecise entry to Debug state and clear sticky bits in EDSCR.

This register is part of the Debug registers functional group.

Usage constraints

This register is accessible as follows:

Off DLK OSLK SLK Default
Error Error Error WI WO
Configurations

EDRCR is in the Core power domain.

Attributes

See C7.1 Memory-mapped debug register summary.

EDRCR is a 32-bit register.

Figure C7-1 EDRCR bit assignments
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[31:5]

Reserved, res0.

CBRRQ, [4]

Allow imprecise entry to Debug state. The actions on writing to this bit are:

0No action.
1Allow imprecise entry to Debug state, for example by canceling pending bus accesses. Setting this bit to 1 allows a debugger to request imprecise entry to Debug state. An External Debug Request debug event must be pending before the debugger sets this bit to 1.
CSPA, [3]

Clear Sticky Pipeline Advance. This bit is used to clear the EDSCR.PipeAdv bit to 0. The actions on writing to this bit are:

0No action.
1Clear the EDSCR.PipeAdv bit to 0.
CSE, [2]

Clear Sticky Error. Used to clear the EDSCR cumulative error bits to 0. The actions on writing to this bit are:

0No action
1Clear the EDSCR.{TXU, RXO, ERR} bits, and, if the processor is in Debug state, the EDSCR.ITO bit, to 0.
[1:0]

Reserved, res0.

The EDRCR can be accessed through the external debug interface, offset 0x090.

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