C7.3 External Debug Integration Mode Control Register

The EDITCTRL characteristics are:

Purpose
Enables the external debug to switch from its default mode into integration mode, where test software can control directly the inputs and outputs of the processor, for integration testing or topology detection.
Usage constraints

This register is accessible as follows:

Off DLK OSLK EDAD SLK Default
- - - - RO RW

Table C1-1 Conditions on external register access to debug registers describes the condition codes.

Configurations
EDITCTRL is in the processor power domain.
Attributes
See C7.1 Memory-mapped debug register summary.
Figure C7-2 EDITCTRL bit assignments
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[31:1]

Reserved, res0.

IME, [0]

Integration Mode Enable.

res0.The device does not revert to an integration mode to enable integration testing or topology detection.

The EDITCTRL can be accessed through the external debug interface, offset 0xF00.

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