C7.18 External Debug Component Identification Register 1

The EDCIDR1 characteristics are:

Purpose
Provides information to identify an external debug component.
Usage constraints

This register is accessible as follows:

Off DLK OSLK EDAD SLK Default
- - - - - RO

Table C1-1 Conditions on external register access to debug registers describes the condition codes.

Configurations
The EDCIDR1 is in the Debug power domain.
Attributes
See C7.1 Memory-mapped debug register summary.
Figure C7-14 EDCIDR1 bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


[31:8]

Reserved, res0.

CLASS, [7:4]
0x9Debug component.
PRMBL_1, [3:0]
0x0Preamble.

The EDCIDR1 can be accessed through the external debug interface, offset 0xFF4.

Non-ConfidentialPDF file icon PDF versionARM 100241_0001_00_en
Copyright © 2016, 2017 ARM Limited or its affiliates. All rights reserved.