C8.5 ROM Table Peripheral Identification Registers

The ROM Table Peripheral Identification Registers provide standard information required for all components that conform to the ARM Debug Interface Architecture Specification, ADIv5.0 to ADIv5.2.

There are eight registers listed in register number order in the following table.

Table C8-4 Summary of the ROM Table Peripheral Identification Registers

Register Value Offset
ROMPIDR4 0x04 0xFD0
ROMPIDR5 0x00 0xFD4
ROMPIDR6 0x00 0xFD8
ROMPIDR7 0x00 0xFDC
ROMPIDR0

0xAB for v8 memory map.

0xE1 for v7 memory map.

0xFE0
ROMPIDR1 0xB4 0xFE4
ROMPIDR2 0x1B 0xFE8
ROMPIDR3 0x00 0xFEC

Only bits[7:0] of each Peripheral ID Register are used, with bits[31:8] reserved. Together, the eight Peripheral ID Registers define a single 64-bit Peripheral ID.

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