B2.1 CPU interface register summary

Each CPU interface block provides the interface for a Cortex®‑A32 processor that interfaces with a GIC distributor within the system.

Each CPU interface provides a programming interface for:

  • Enabling the signaling of interrupt requests by the CPU interface.
  • Acknowledging an interrupt.
  • Indicating completion of the processing of an interrupt.
  • Setting an interrupt priority mask for the processor.
  • Defining the preemption policy for the processor.
  • Determining the highest priority pending interrupt for the processor.
  • Generating SGIs.

For more information on the CPU interface, see the ARM® Generic Interrupt Controller Architecture Specification.

The following table lists the registers for the CPU interface.

All the registers in the following table are word-accessible. Registers not described in this table are res0. See the ARM® Generic Interrupt Controller Architecture Specification for more information.

Table B2-1 CPU interface register summary

Offset Name Type Reset Description
0x0000 GICC_CTLR RW 0x00000000 CPU Interface Control Register
0x0004 GICC_PMR RW 0x00000000 Interrupt Priority Mask Register
0x0008 GICC_BPR RW

0x00000002 (Secure)

0x00000003 (Non-secure)

Binary Point Register
0x000C GICC_IAR RO - Interrupt Acknowledge Register
0x0010 GICC_EOIR WO - End Of Interrupt Register
0x0014 GICC_RPR RO 0x000000FF Running Priority Register
0x0018 GICC_HPPIR RO 0x000003FF Highest Priority Pending Interrupt Register
0x001C GICC_ABPR RW 0x00000003 Aliased Binary Point Register
0x0020 GICC_AIAR RO -

Aliased Interrupt Acknowledge Register

0x0024 GICC_AEOIR WO -

Aliased End of Interrupt Register

0x0028 GICC_AHPPIR RO 0x000003FF

Aliased Highest Priority Pending Interrupt Register

0x00D0 GICC_APR0 RW 0x00000000 B2.2 Active Priority Register
0x00E0 GICC_NSAPR0 RW 0x00000000 Non-secure Active Priority Register
0x00FC GICC_IIDR RO 0x0014143B B2.3 CPU Interface Identification Register
0x1000 GICC_DIR WO - Deactivate Interrupt Register
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