B2.2 Active Priority Register

The GICC_APR0 characteristics are:

Provides support for preserving and restoring state in power management applications.
Usage constraints
This register is banked to provide Secure and Non-secure copies. This ensures that Non-secure accesses do not interfere with Secure operation.
Available in all configurations.
See the register summary in B2.1 CPU interface register summary.

The Cortex®‑A32 processor implements the GICC_APR0 according to the recommendations described in the ARM Generic Interrupt Controller Architecture Specification.

Table B2-2 Active Priority Register implementation

Number of group priority bits Preemption levels Minimum value of Secure GICC_BPR Minimum legal value of Non-secure GICC_BPR Active Priority Registers implemented View of Active Priority Registers for Non-secure accesses
5 32 2 3 GICC_APR0 [31:0] GICC_NSAPR0 [31:16] appears as GICC_APRo [15:0]
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