B2.4 Virtual interface control register summary

The virtual interface control registers are management registers. Configuration software on the Cortex®‑A32 processor must ensure they are accessible only by a hypervisor, or similar software.

The following table describes the registers for the virtual interface control registers. All these registers are word-accessible. Registers not described in this table are res0. See the ARM® Generic Interrupt Controller Architecture Specification for more information.

Table B2-3 Virtual interface control register summary

Offset Name Type Reset Description
0x000 GICH_HCR RW 0x00000000 Hypervisor Control Register
0x004 GICH_VTR RO 0x90000003 B2.5 VGIC Type Register
0x008 GICH_VMCR RW 0x004C0000

Virtual Machine Control Register

0x010 GICH_MISR RO 0x00000000

Maintenance Interrupt Status Register

0x020 GICH_EISR0 RO 0x00000000

End of Interrupt Status Registers

0x030 GICH_ELRSR0 RO 0x0000000F

Empty List Register Status Registers

0x0F0 GICH_APR0 RW 0x00000000 Active Priorities Register
0x100 GICH_LR0 RW 0x00000000 List Register 0
0x104 GICH_LR1 RW 0x00000000 List Register 1
0x108 GICH_LR2 RW 0x00000000 List Register 2
0x10C GICH_LR3 RW 0x00000000 List Register 3
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