C9.2 Performance Monitors Control Register

The PMCR characteristics are:

Purpose
Provides details of the Performance Monitors implementation, including the number of counters implemented, and configures and controls the counters.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

Config Config RW RW RW RW RW

This register is accessible at EL0 when PMUSERENR_EL0.EN is set to 1.

Configurations

PMCR[6:0] is architecturally mapped to external PMCR_EL0 register.

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes
PMCR is a 32-bit register.
Figure C9-1 PMCR bit assignments
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IMP, [31:24]

Implementer code:

0x41ARM.

This is a read-only field.

IDCODE, [23:16]

Identification code:

0x06Cortex®‑A32.

This is a read-only field.

N, [15:11]

Number of event counters.

0b00110Six counters.
[10:7]

Reserved, res0.

LC, [6]

Long cycle count enable. Determines which PMCCNTR bit generates an overflow recorded in PMOVSR[31]. The possible values are:

0Overflow on increment that changes PMCCNTR[31] from 1 to 0.
1Overflow on increment that changes PMCCNTR[63] from 1 to 0.
DP, [5]

Disable cycle counter, PMCCNTR when event counting is prohibited:

0Cycle counter operates regardless of the non-invasive debug authentication settings. This is the reset value.
1Cycle counter is disabled if non-invasive debug is not permitted and enabled.

This bit is read/write.

X, [4]

Export enable. This bit permits events to be exported to another debug device, such as a trace macrocell, over an event bus:

0Export of events is disabled. This is the reset value.
1Export of events is enabled.

This bit is read/write and does not affect the generation of Performance Monitors interrupts on the nPMUIRQ pin.

D, [3]

Clock divider:

0When enabled, PMCCNTR counts every clock cycle. This is the reset value.
1When enabled, PMCCNTR counts every 64 clock cycles.

This bit is read/write.

C, [2]

Clock counter reset. This bit is WO. The effects of writing to this bit are:

0No action. This is the reset value.
1Reset PMCCNTR_EL0 to 0.

This bit is always RAZ.

Resetting PMCCNTR does not clear the PMCCNTR overflow bit to 0. See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information.

P, [1]

Event counter reset. This bit is WO. The effects of writing to this bit are:

0No action. This is the reset value.
1Reset all event counters, not including PMCCNTR, to zero.

This bit is always RAZ.

In Non-secure EL0 and EL1, a write of 1 to this bit does not reset event counters that HDCR.HPMN reserves for EL2 use.

In EL2 and EL3, a write of 1 to this bit resets all the event counters.

Resetting the event counters does not clear any overflow bits to 0.

E, [0]

Enable. The possible values of this bit are:

0All counters, including PMCCNTR, are disabled. This is the reset value.
1All counters are enabled.

This bit is RW.

In Non-secure EL0 and EL1, this bit does not affect the operation of event counters that HDCR_EL2.HPMN reserves for EL2 use.

On Warm reset, the field resets to 0.

To access the PMCR:

MRC p15, 4, <Rt>, c12, c0, 0 ; Read PMCR into Rt
MCR p15, 4, <Rt>, c12, c0, 0 ; Write Rt to PMCR

The PMCR can be accessed through the external debug interface, offset 0xE04.

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