C9.4 Performance Monitors Common Event Identification Register 1

The PMCEID1 characteristics are:

Purpose
Defines which common architectural and common microarchitectural feature events are implemented.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

Config Config RO RO RO RO RO

This register is accessible at EL0 when PMUSERENR_EL0.EN is set to 1

Configurations

The PMCEID1 is architecturally mapped to the external register PMCEID1_EL0.

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes
PMCEID1 is a 32-bit register.
Figure C9-3 PMCEID1 bit assignments
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[31:17]
CE[48:32], [16:0]

Common architectural and microarchitectural feature events that can be counted by the PMU event counters.

For each bit described in The following table, the event is implemented if the bit is set to 1, or not implemented if the bit is set to 0.

Table C9-3 PMU common events

Bit Event number Event mnemonic Description
[16] 0x30 L2I_TLB

Attributable Level 2 instruction TLB access.

0This event is not implemented.
[15] 0x2F

L2D_TLB

Attributable Level 2 data or unified TLB access.

0This event is not implemented.
[14] 0x2E

L2I_TLB_REFILL

Attributable Level 2 instruction TLB refill.

0This event is not implemented.
[13] 0x2D

L2D_TLB_REFIL

Attributable Level 2 data or unified TLB refill.

0This event is not implemented.
[12] 0x2C

L3D_CACHE_WB

Attributable Level 3 data or unified cache write-back.

0This event is not implemented.
[11] 0x2B

L3D_CACHE

Attributable Level 3 data or unified cache access.

0This event is not implemented.
[10] 0x2A

L3D_CACHE_REFILL

Attributable Level 3 data or unified cache refill.

0This event is not implemented.
[9] 0x29

L3D_CACHE_ALLOCATE

Attributable Level 3 data or unified cache allocation without refill.

0This event is not implemented.
[8] 0x28

L2I_CACHE_REFILL

Attributable Level 2 instruction cache refill.

0This event is not implemented.
[7] 0x27

L2I_CACHE

Attributable Level 2 instruction cache access.

0This event is not implemented.
[6] 0x26

L1I_TLB

Level 1 instruction TLB access.

0This event is not implemented.
[5] 0x25

L1D_TLB

Level 1 data or unified TLB access.

0This event is not implemented.
[4] 0x24

STALL_BACKEND

No operation issued due to backend.

0This event is not implemented.
[3] 0x23

STALL_FRONTEND

No operation issued due to the frontend.

0This event is not implemented.
[2] 0x22

BR_MIS_PRED_RETIRED

Instruction architecturally executed, mispredicted branch.

0This event is not implemented.
[1] 0x21

BR_RETIRED

Instruction architecturally executed, branch.

0This event is not implemented.
[0] 0x20

L2D_CACHE_ALLOCATE

Level 2 data cache allocation without refill.

0This event is not implemented.

To access the PMCEID1:

MRC p15,0,<Rt>,c9,c12,7 ; Read PMCEID1 into Rt

The PMCEID1 can be accessed through the external debug interface, offset 0xE24.

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