C9.5 Memory-mapped PMU register summary

There are PMU registers that are accessible through the external debug interface.

These registers are listed in the following table. For those registers not described in this chapter, see the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.

Table C9-4 Memory-mapped PMU register summary

Offset Name Type Description
0x000 PMEVCNTR0_EL0 RW

Performance Monitors Event Count Register 0

0x004 - - Reserved
0x008 PMEVCNTR1_EL0 RW

Performance Monitors Event Count Register 1

0x00C - - Reserved
0x010 PMEVCNTR2_EL0 RW

Performance Monitors Event Count Register 2

0x014 - - Reserved
0x018 PMEVCNTR3_EL0 RW

Performance Monitors Event Count Register 3

0x01C - - Reserved
0x020 PMEVCNTR4_EL0 RW

Performance Monitors Event Count Register 4

0x024 - - Reserved
0x028 PMEVCNTR5_EL0 RW

Performance Monitors Event Count Register 5

0x02C-0xF4 - - Reserved
0x0F8 PMCCNTR_EL0[31:0] RW

Performance Monitors Cycle Count Register

0x0FC PMCCNTR_EL0[63:32] RW
0x100-0x3FC - - Reserved
0x400 PMEVTYPER0_EL0 RW Performance Monitors Event Type Register
0x404 PMEVTYPER1_EL0 RW
0x408 PMEVTYPER2_EL0 RW
0x40C PMEVTYPER3_EL0 RW
0x410 PMEVTYPER4_EL0 RW
0x414 PMEVTYPER5_EL0 RW
0x418-0x478 - - Reserved
0x47C PMCCFILTR_EL0 RW

Performance Monitors Cycle Count Filter Register

0x480-0xBFC - - Reserved
0xC00 PMCNTENSET_EL0 RW

Performance Monitors Count Enable Set Register

0xC04-0xC1C - - Reserved
0xC20 PMCNTENCLR_EL0 RW

Performance Monitors Count Enable Clear Register

0xC24-0xC3C - - Reserved
0xC40 PMINTENSET_EL1 RW

Performance Monitor Interrupt Enable Set Register

0xC44-0xC5C - - Reserved
0xC60 PMINTENCLR_EL1 RW

Performance Monitors Interrupt Enable Clear Register

0xC64-0xC7C - - Reserved
0xC80 PMOVSCLR_EL0 RW

Performance Monitors Overflow Flag Status Register

0xC84-0xC9C - - Reserved
0xCA0 PMSWINC_EL0 WO

Performance Monitor Software Increment Register

0xCA4-0xCBC - - Reserved
0xCC0 PMOVSSET_EL0 RW Performance Monitors Overflow Flag Status Set Register
0xCC4-0xDFC - - Reserved
0xE00 PMCFGR RO C9.6 Performance Monitors Configuration Register
0xE04 PMCR_EL0 RW

Performance Monitors Control Register

0xE08-0xE1C - - Reserved
0xE20 PMCEID0_EL0 RO C9.3 Performance Monitors Common Event Identification Register 0
0xE24 PMCEID1_EL0 RO C9.4 Performance Monitors Common Event Identification Register 1
0xE28-0xFA4 - - Reserved
0xFA8 PMDEVAFF0 RO Performance Monitors Device Affinity Register 0, see B1.97 Multiprocessor Affinity Register
0xFAC PMDEVAFF1 RO Performance Monitors Device Affinity Register 1, res0
0xFB0 PMLAR WO

Performance Monitors Lock Access Register

0xFB4 PMLSR RO Performance Monitors Lock Status Register
0xFB8 PMAUTHSTATUS RO

Performance Monitors Authentication Status Register

0xFBC PMDEVARCH   Performance Monitors Device Architecture Register
0xFC0-0xFC8 - - Reserved
0xFCC PMDEVTYPE RO

Performance Monitors Device Type Register

0xFD0 PMPIDR4 RO C9.12 Performance Monitors Peripheral Identification Register 4
0xFD4 PMPIDR5 RO C9.13 Performance Monitors Peripheral Identification Register 5-7
0xFD8 PMPIDR6 RO
0xFDC PMPIDR7 RO
0xFE0 PMPIDR0 RO C9.8 Performance Monitors Peripheral Identification Register 0
0xFE4 PMPIDR1 RO C9.9 Performance Monitors Peripheral Identification Register 1
0xFE8 PMPIDR2 RO C9.10 Performance Monitors Peripheral Identification Register 2
0xFEC PMPIDR3 RO C9.11 Performance Monitors Peripheral Identification Register 3
0xFF0 PMCIDR0 RO C9.15 Performance Monitors Component Identification Register 0
0xFF4 PMCIDR1 RO C9.16 Performance Monitors Component Identification Register 1
0xFF8 PMCIDR2 RO C9.17 Performance Monitors Component Identification Register 2
0xFFC PMCIDR3 RO C9.18 Performance Monitors Component Identification Register 3
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